From 5c4c107eaf077a75ca17b425c2a9fd570c99923b Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Wed, 11 Oct 2023 09:01:56 -0700 Subject: [PATCH] add sh7091 and holly registers --- .gitignore | 3 + holly.h | 166 +++++++++++++++++++ regs/gen/generate.py | 25 +++ regs/gen/holly.py | 18 +++ regs/gen/sh7091.py | 160 ++++++++++++++++++ regs/holly.csv | 87 ++++++++++ regs/holly.ods | Bin 0 -> 23465 bytes regs/sh7091.csv | 126 +++++++++++++++ regs/sh7091.ods | Bin 0 -> 21788 bytes sh7091.h | 376 +++++++++++++++++++++++++++++++++++++++++++ type.h | 16 ++ 11 files changed, 977 insertions(+) create mode 100644 .gitignore create mode 100644 holly.h create mode 100644 regs/gen/generate.py create mode 100644 regs/gen/holly.py create mode 100644 regs/gen/sh7091.py create mode 100644 regs/holly.csv create mode 100644 regs/holly.ods create mode 100644 regs/sh7091.csv create mode 100644 regs/sh7091.ods create mode 100644 sh7091.h create mode 100644 type.h diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a1e7a31 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.pyc +__pycache__ +.~* \ No newline at end of file diff --git a/holly.h b/holly.h new file mode 100644 index 0000000..bd3a9f4 --- /dev/null +++ b/holly.h @@ -0,0 +1,166 @@ +#include +#include + +struct holly_reg { + uint32_t ID; /* Device ID */ + uint32_t REVISION; /* Revision Number */ + uint32_t SOFTRESET; /* CORE & TA software reset */ + uint8_t _pad0[8]; + uint32_t STARTRENDER; /* Drawing start */ + uint32_t TEST_SELECT; /* Test (writing this register is prohibited) */ + uint8_t _pad1[4]; + uint32_t PARAM_BASE; /* Base address for ISP parameters */ + uint8_t _pad2[8]; + uint32_t REGION_BASE; /* Base address for Region Array */ + uint32_t SPAN_SORT_CFG; /* Span Sorter control */ + uint8_t _pad3[12]; + uint32_t VO_BORDER_COL; /* Border area color */ + uint32_t FB_R_CTRL; /* Frame buffer read control */ + uint32_t FB_W_CTRL; /* Frame buffer write control */ + uint32_t FB_W_LINESTRIDE;/* Frame buffer line stride */ + uint32_t FB_R_SOF1; /* Read start address for field - 1/strip - 1 */ + uint32_t FB_R_SOF2; /* Read start address for field - 2/strip - 2 */ + uint8_t _pad4[4]; + uint32_t FB_R_SIZE; /* Frame buffer XY size */ + uint32_t FB_W_SOF1; /* Write start address for field - 1/strip - 1 */ + uint32_t FB_W_SOF2; /* Write start address for field - 2/strip - 2 */ + uint32_t FB_X_CLIP; /* Pixel clip X coordinate */ + uint32_t FB_Y_CLIP; /* Pixel clip Y coordinate */ + uint8_t _pad5[4]; + uint32_t FPU_SHAD_SCALE; /* Intensity Volume mode */ + uint32_t FPU_CULL_VAL; /* Comparison value for culling */ + uint32_t FPU_PARAM_CFG; /* Parameter read control */ + uint32_t HALF_OFFSET; /* Pixel sampling control */ + uint32_t FPU_PERP_VAL; /* Comparison value for perpendicular polygons */ + uint32_t ISP_BACKGND_D; /* Background surface depth */ + uint32_t ISP_BACKGND_T; /* Background surface tag */ + uint8_t _pad6[8]; + uint32_t ISP_FEED_CFG; /* Translucent polygon sort mode */ + uint8_t _pad7[4]; + uint32_t SDRAM_REFRESH; /* Texture memory refresh counter */ + uint32_t SDRAM_ARB_CFG; /* Texture memory arbiter control */ + uint32_t SDRAM_CFG; /* Texture memory control */ + uint8_t _pad8[4]; + uint32_t FOG_COL_RAM; /* Color for Look Up table Fog */ + uint32_t FOG_COL_VERT; /* Color for vertex Fog */ + uint32_t FOG_DENSITY; /* Fog scale value */ + uint32_t FOG_CLAMP_MAX; /* Color clamping maximum value */ + uint32_t FOG_CLAMP_MIN; /* Color clamping minimum value */ + uint32_t SPG_TRIGGER_POS;/* External trigger signal HV counter value */ + uint32_t SPG_HBLANK_INT; /* H-blank interrupt control */ + uint32_t SPG_VBLANK_INT; /* V-blank interrupt control */ + uint32_t SPG_CONTROL; /* Sync pulse generator control */ + uint32_t SPG_HBLANK; /* H-blank control */ + uint32_t SPG_LOAD; /* HV counter load value */ + uint32_t SPG_VBLANK; /* V-blank control */ + uint32_t SPG_WIDTH; /* Sync width control */ + uint32_t TEXT_CONTROL; /* Texturing control */ + uint32_t VO_CONTROL; /* Video output control */ + uint32_t VO_STARTX; /* Video output start X position */ + uint32_t VO_STARTY; /* Video output start Y position */ + uint32_t SCALER_CTL; /* X & Y scaler control */ + uint8_t _pad9[16]; + uint32_t PAL_RAM_CTRL; /* Palette RAM control */ + uint32_t SPG_STATUS; /* Sync pulse generator status */ + uint32_t FB_BURSTCTRL; /* Frame buffer burst control */ + uint32_t FB_C_SOF; /* Current frame buffer start address */ + uint32_t Y_COEFF; /* Y scaling coefficent */ + uint32_t PT_ALPHA_REF; /* Alpha value for Punch Through polygon comparison */ + uint8_t _pad10[4]; + uint32_t TA_OL_BASE; /* Object List write start address */ + uint32_t TA_ISP_BASE; /* ISP/TSP Parameter write start address */ + uint32_t TA_OL_LIMIT; /* Object List write limit address */ + uint32_t TA_ISP_LIMIT; /* ISP/TSP Parameter limit address */ + uint32_t TA_NEXT_OPB; /* Start address for the Object Pointer Block */ + uint32_t TA_ITP_CURRENT; /* Starting address where the next ISP/TSP Parameters are stored */ + uint32_t TA_GLOB_TILE_CLIP;/* Global Tile Clip control */ + uint32_t TA_ALLOC_CTRL; /* Object list control */ + uint32_t TA_LIST_INIT; /* TA initialization */ + uint32_t TA_YUV_TEX_BASE;/* YUV422 texture write start address */ + uint32_t TA_YUV_TEX_CTRL;/* YUV converter control */ + uint32_t TA_YUV_TEX_CNT; /* YUV converter macro block counter value */ + uint8_t _pad11[12]; + uint32_t TA_LIST_CONT; /* TA continuation processing */ + uint32_t TA_NEXT_OPB_INIT;/* Additional OPB starting address */ + uint8_t _pad12[152]; + uint8_t FOG_TABLE[512]; /* Look-up table fog data */ + uint8_t _pad13[512]; + uint8_t TA_OL_POINTERS[2400];/* TA Object List Pointer data */ + uint8_t _pad14[160]; + uint8_t PALETTE_RAM[4096];/* Palette RAM */ +}; + +static_assert((offsetof (struct holly_reg, ID)) == 0x0); +static_assert((offsetof (struct holly_reg, REVISION)) == 0x4); +static_assert((offsetof (struct holly_reg, SOFTRESET)) == 0x8); +static_assert((offsetof (struct holly_reg, STARTRENDER)) == 0x14); +static_assert((offsetof (struct holly_reg, TEST_SELECT)) == 0x18); +static_assert((offsetof (struct holly_reg, PARAM_BASE)) == 0x20); +static_assert((offsetof (struct holly_reg, REGION_BASE)) == 0x2c); +static_assert((offsetof (struct holly_reg, SPAN_SORT_CFG)) == 0x30); +static_assert((offsetof (struct holly_reg, VO_BORDER_COL)) == 0x40); +static_assert((offsetof (struct holly_reg, FB_R_CTRL)) == 0x44); +static_assert((offsetof (struct holly_reg, FB_W_CTRL)) == 0x48); +static_assert((offsetof (struct holly_reg, FB_W_LINESTRIDE)) == 0x4c); +static_assert((offsetof (struct holly_reg, FB_R_SOF1)) == 0x50); +static_assert((offsetof (struct holly_reg, FB_R_SOF2)) == 0x54); +static_assert((offsetof (struct holly_reg, FB_R_SIZE)) == 0x5c); +static_assert((offsetof (struct holly_reg, FB_W_SOF1)) == 0x60); +static_assert((offsetof (struct holly_reg, FB_W_SOF2)) == 0x64); +static_assert((offsetof (struct holly_reg, FB_X_CLIP)) == 0x68); +static_assert((offsetof (struct holly_reg, FB_Y_CLIP)) == 0x6c); +static_assert((offsetof (struct holly_reg, FPU_SHAD_SCALE)) == 0x74); +static_assert((offsetof (struct holly_reg, FPU_CULL_VAL)) == 0x78); +static_assert((offsetof (struct holly_reg, FPU_PARAM_CFG)) == 0x7c); +static_assert((offsetof (struct holly_reg, HALF_OFFSET)) == 0x80); +static_assert((offsetof (struct holly_reg, FPU_PERP_VAL)) == 0x84); +static_assert((offsetof (struct holly_reg, ISP_BACKGND_D)) == 0x88); +static_assert((offsetof (struct holly_reg, ISP_BACKGND_T)) == 0x8c); +static_assert((offsetof (struct holly_reg, ISP_FEED_CFG)) == 0x98); +static_assert((offsetof (struct holly_reg, SDRAM_REFRESH)) == 0xa0); +static_assert((offsetof (struct holly_reg, SDRAM_ARB_CFG)) == 0xa4); +static_assert((offsetof (struct holly_reg, SDRAM_CFG)) == 0xa8); +static_assert((offsetof (struct holly_reg, FOG_COL_RAM)) == 0xb0); +static_assert((offsetof (struct holly_reg, FOG_COL_VERT)) == 0xb4); +static_assert((offsetof (struct holly_reg, FOG_DENSITY)) == 0xb8); +static_assert((offsetof (struct holly_reg, FOG_CLAMP_MAX)) == 0xbc); +static_assert((offsetof (struct holly_reg, FOG_CLAMP_MIN)) == 0xc0); +static_assert((offsetof (struct holly_reg, SPG_TRIGGER_POS)) == 0xc4); +static_assert((offsetof (struct holly_reg, SPG_HBLANK_INT)) == 0xc8); +static_assert((offsetof (struct holly_reg, SPG_VBLANK_INT)) == 0xcc); +static_assert((offsetof (struct holly_reg, SPG_CONTROL)) == 0xd0); +static_assert((offsetof (struct holly_reg, SPG_HBLANK)) == 0xd4); +static_assert((offsetof (struct holly_reg, SPG_LOAD)) == 0xd8); +static_assert((offsetof (struct holly_reg, SPG_VBLANK)) == 0xdc); +static_assert((offsetof (struct holly_reg, SPG_WIDTH)) == 0xe0); +static_assert((offsetof (struct holly_reg, TEXT_CONTROL)) == 0xe4); +static_assert((offsetof (struct holly_reg, VO_CONTROL)) == 0xe8); +static_assert((offsetof (struct holly_reg, VO_STARTX)) == 0xec); +static_assert((offsetof (struct holly_reg, VO_STARTY)) == 0xf0); +static_assert((offsetof (struct holly_reg, SCALER_CTL)) == 0xf4); +static_assert((offsetof (struct holly_reg, PAL_RAM_CTRL)) == 0x108); +static_assert((offsetof (struct holly_reg, SPG_STATUS)) == 0x10c); +static_assert((offsetof (struct holly_reg, FB_BURSTCTRL)) == 0x110); +static_assert((offsetof (struct holly_reg, FB_C_SOF)) == 0x114); +static_assert((offsetof (struct holly_reg, Y_COEFF)) == 0x118); +static_assert((offsetof (struct holly_reg, PT_ALPHA_REF)) == 0x11c); +static_assert((offsetof (struct holly_reg, TA_OL_BASE)) == 0x124); +static_assert((offsetof (struct holly_reg, TA_ISP_BASE)) == 0x128); +static_assert((offsetof (struct holly_reg, TA_OL_LIMIT)) == 0x12c); +static_assert((offsetof (struct holly_reg, TA_ISP_LIMIT)) == 0x130); +static_assert((offsetof (struct holly_reg, TA_NEXT_OPB)) == 0x134); +static_assert((offsetof (struct holly_reg, TA_ITP_CURRENT)) == 0x138); +static_assert((offsetof (struct holly_reg, TA_GLOB_TILE_CLIP)) == 0x13c); +static_assert((offsetof (struct holly_reg, TA_ALLOC_CTRL)) == 0x140); +static_assert((offsetof (struct holly_reg, TA_LIST_INIT)) == 0x144); +static_assert((offsetof (struct holly_reg, TA_YUV_TEX_BASE)) == 0x148); +static_assert((offsetof (struct holly_reg, TA_YUV_TEX_CTRL)) == 0x14c); +static_assert((offsetof (struct holly_reg, TA_YUV_TEX_CNT)) == 0x150); +static_assert((offsetof (struct holly_reg, TA_LIST_CONT)) == 0x160); +static_assert((offsetof (struct holly_reg, TA_NEXT_OPB_INIT)) == 0x164); +static_assert((offsetof (struct holly_reg, FOG_TABLE)) == 0x200); +static_assert((offsetof (struct holly_reg, TA_OL_POINTERS)) == 0x600); +static_assert((offsetof (struct holly_reg, PALETTE_RAM)) == 0x1000); + +extern holly_reg HOLLY; + diff --git a/regs/gen/generate.py b/regs/gen/generate.py new file mode 100644 index 0000000..8ac8aa4 --- /dev/null +++ b/regs/gen/generate.py @@ -0,0 +1,25 @@ +import io + +def _render(out, lines): + indent = " " + level = 0 + for l in lines: + if l and (l[0] == "}" or l[0] == ")"): + level -= 2 + assert level >= 0, out.getvalue() + + out.write(indent * level + l + "\n") + + if l and (l[-1] == "{" or l[-1] == "("): + level += 2 + + if level == 0 and l and l[-1] == ";": + if "static_assert" not in l: + out.write("\n") + return out + +def renderer(): + out = io.StringIO() + def render(lines): + return _render(out, lines) + return render, out diff --git a/regs/gen/holly.py b/regs/gen/holly.py new file mode 100644 index 0000000..c42d9f1 --- /dev/null +++ b/regs/gen/holly.py @@ -0,0 +1,18 @@ +import sys + +from sh7091 import new_writer +from sh7091 import read_input +from sh7091 import headers +from generate import renderer + +def block(): + yield "extern holly_reg HOLLY;" + +input_file = sys.argv[1] +rows = read_input(input_file) +process = new_writer() +render, out = renderer() +render(headers()) +render(process(rows)) +render(block()) +sys.stdout.write(out.getvalue()) diff --git a/regs/gen/sh7091.py b/regs/gen/sh7091.py new file mode 100644 index 0000000..447cf4a --- /dev/null +++ b/regs/gen/sh7091.py @@ -0,0 +1,160 @@ +import csv +import sys +from functools import partial +from pprint import pprint + +from generate import renderer + +def as_dict(header, row): + return dict(zip(header, row)) + +def read_input(filename): + with open(filename) as f: + reader = csv.reader(f, delimiter=",", quotechar='"') + header, *rows = reader + + rows = [ + as_dict(header, row) + for row in rows + if "".join(map(str, row)).strip() + ] + + return rows + +def size_p(size): + return size in {1, 2, 4} + +def size_to_type(size): + if size == 1: + return "uint8_t " + elif size == 2: + return "uint16_t" + elif size == 4: + return "uint32_t" + else: + raise NotImplemented(size) + +def new_writer(): + first_address = 0 + last_address = 0 + last_block = None + size_total = 0 + reserved_num = 0 + stack = [] + + def terminate(): + nonlocal last_block + nonlocal first_address + nonlocal stack + + if last_block is not None: + yield "};" + for address, name in stack: + relative_address = address - first_address + yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(relative_address)});" + yield "" + stack = [] + + def process_row(row): + nonlocal first_address + nonlocal last_address + nonlocal last_block + nonlocal reserved_num + nonlocal size_total + nonlocal stack + + block = row["block"] + _offset = int(row["offset"], 16) if "offset" in row else 0 + _address = int(row["address"], 16) + assert _offset <= 0xff + assert _address <= 0xffff + address = (_offset << 16) | (_address << 0) + size = int(row["size"], 10) + name = row["name"] + description = row["description"] + + if block != last_block: + yield from terminate() + first_address = address + last_address = address + size_total = 0 + reserved_num = 0 + yield f"struct {block.lower()}_reg {{" + + if address != last_address: + padding = address - last_address + assert padding > 0, (row, address, last_address) + type = size_to_type(1) + yield f"{type} _pad{reserved_num}[{padding}];" + reserved_num += 1 + size_total += padding + + def field(): + if size_p(size): + assert address % size == 0 + type = size_to_type(size) + return f"{type} {name};" + else: + type = size_to_type(1) + return f"{type} {name}[{size}];" + + yield field().ljust(25) + f"/* {description} */" + + stack.append((address, name)) + last_address = address + size + last_block = block + size_total += size + + def process(rows): + for row in rows: + yield from process_row(row) + yield from terminate() + + return process + +def blocks(rows): + stack = [] + last_block = None + for row in rows: + block = row["block"] + if last_block != block: + offset = int(row["offset"], 16) + stack.append((block, offset)) + last_block = block + + yield "struct sh7091_reg {" + last_offset = 0 + last_block = None + reserved_num = 0 + for block, offset in stack: + if offset != last_offset: + assert last_block is not None + type = size_to_type(1) + raw_pad = (offset - last_offset) << 16 + yield f"{type} _pad{reserved_num}[{hex(raw_pad)} - (sizeof (struct {last_block.lower()}_reg))];" + reserved_num += 1 + yield f"{block.lower()}_reg {block};" + last_offset = offset + last_block = block + yield "};" + + for block, offset in stack: + yield f"static_assert((offsetof (struct sh7091_reg, {block})) == {hex(offset << 16)});" + + yield "" + yield "extern sh7091_reg SH7091;" + +def headers(): + yield "#include " + yield "#include " + yield "" + +if __name__ == "__main__": + input_file = sys.argv[1] + rows = read_input(input_file) + process = new_writer() + render, out = renderer() + render(headers()) + render(process(rows)) + render(blocks(rows)) + sys.stdout.write(out.getvalue()) diff --git a/regs/holly.csv b/regs/holly.csv new file mode 100644 index 0000000..353e47e --- /dev/null +++ b/regs/holly.csv @@ -0,0 +1,87 @@ +"block","address","size","name","r/w","description" +"holly","0000","4","ID","R","Device ID" +"holly","0004","4","REVISION","R","Revision Number" +"holly","0008","4","SOFTRESET","RW","CORE & TA software reset" +,,,,, +"holly","0014","4","STARTRENDER","RW","Drawing start" +"holly","0018","4","TEST_SELECT","RW","Test (writing this register is prohibited)" +,,,,, +"holly","0020","4","PARAM_BASE","RW","Base address for ISP parameters" +,,,,, +"holly","002c","4","REGION_BASE","RW","Base address for Region Array" +"holly","0030","4","SPAN_SORT_CFG","RW","Span Sorter control" +,,,,, +"holly","0040","4","VO_BORDER_COL","RW","Border area color" +"holly","0044","4","FB_R_CTRL","RW","Frame buffer read control" +"holly","0048","4","FB_W_CTRL","RW","Frame buffer write control" +"holly","004c","4","FB_W_LINESTRIDE","RW","Frame buffer line stride" +"holly","0050","4","FB_R_SOF1","RW","Read start address for field - 1/strip - 1" +"holly","0054","4","FB_R_SOF2","RW","Read start address for field - 2/strip - 2" +,,,,, +"holly","005c","4","FB_R_SIZE","RW","Frame buffer XY size" +"holly","0060","4","FB_W_SOF1","RW","Write start address for field - 1/strip - 1" +"holly","0064","4","FB_W_SOF2","RW","Write start address for field - 2/strip - 2" +"holly","0068","4","FB_X_CLIP","RW","Pixel clip X coordinate" +"holly","006c","4","FB_Y_CLIP","RW","Pixel clip Y coordinate" +,,,,, +"holly","0074","4","FPU_SHAD_SCALE","RW","Intensity Volume mode" +"holly","0078","4","FPU_CULL_VAL","RW","Comparison value for culling" +"holly","007c","4","FPU_PARAM_CFG","RW","Parameter read control" +"holly","0080","4","HALF_OFFSET","RW","Pixel sampling control" +"holly","0084","4","FPU_PERP_VAL","RW","Comparison value for perpendicular polygons" +"holly","0088","4","ISP_BACKGND_D","RW","Background surface depth" +"holly","008c","4","ISP_BACKGND_T","RW","Background surface tag" +,,,,, +"holly","0098","4","ISP_FEED_CFG","RW","Translucent polygon sort mode" +,,,,, +"holly","00a0","4","SDRAM_REFRESH","RW","Texture memory refresh counter" +"holly","00a4","4","SDRAM_ARB_CFG","RW","Texture memory arbiter control" +"holly","00a8","4","SDRAM_CFG","RW","Texture memory control" +,,,,, +"holly","00b0","4","FOG_COL_RAM","RW","Color for Look Up table Fog" +"holly","00b4","4","FOG_COL_VERT","RW","Color for vertex Fog" +"holly","00b8","4","FOG_DENSITY","RW","Fog scale value" +"holly","00bc","4","FOG_CLAMP_MAX","RW","Color clamping maximum value" +"holly","00c0","4","FOG_CLAMP_MIN","RW","Color clamping minimum value" +"holly","00c4","4","SPG_TRIGGER_POS","RW","External trigger signal HV counter value" +"holly","00c8","4","SPG_HBLANK_INT","RW","H-blank interrupt control" +"holly","00cc","4","SPG_VBLANK_INT","RW","V-blank interrupt control" +"holly","00d0","4","SPG_CONTROL","RW","Sync pulse generator control" +"holly","00d4","4","SPG_HBLANK","RW","H-blank control" +"holly","00d8","4","SPG_LOAD","RW","HV counter load value" +"holly","00dc","4","SPG_VBLANK","RW","V-blank control" +"holly","00e0","4","SPG_WIDTH","RW","Sync width control" +"holly","00e4","4","TEXT_CONTROL","RW","Texturing control" +"holly","00e8","4","VO_CONTROL","RW","Video output control" +"holly","00ec","4","VO_STARTX","RW","Video output start X position" +"holly","00f0","4","VO_STARTY","RW","Video output start Y position" +"holly","00f4","4","SCALER_CTL","RW","X & Y scaler control" +,,,,, +"holly","0108","4","PAL_RAM_CTRL","RW","Palette RAM control" +"holly","010c","4","SPG_STATUS","R","Sync pulse generator status" +"holly","0110","4","FB_BURSTCTRL","RW","Frame buffer burst control" +"holly","0114","4","FB_C_SOF","R","Current frame buffer start address" +"holly","0118","4","Y_COEFF","RW","Y scaling coefficent" +"holly","011c","4","PT_ALPHA_REF","RW","Alpha value for Punch Through polygon comparison" +,,,,, +"holly","0124","4","TA_OL_BASE","RW","Object List write start address" +"holly","0128","4","TA_ISP_BASE","RW","ISP/TSP Parameter write start address" +"holly","012c","4","TA_OL_LIMIT","RW","Object List write limit address" +"holly","0130","4","TA_ISP_LIMIT","RW","ISP/TSP Parameter limit address" +"holly","0134","4","TA_NEXT_OPB","R","Start address for the Object Pointer Block" +"holly","0138","4","TA_ITP_CURRENT","R","Starting address where the next ISP/TSP Parameters are stored" +"holly","013c","4","TA_GLOB_TILE_CLIP","RW","Global Tile Clip control" +"holly","0140","4","TA_ALLOC_CTRL","RW","Object list control" +"holly","0144","4","TA_LIST_INIT","RW","TA initialization" +"holly","0148","4","TA_YUV_TEX_BASE","RW","YUV422 texture write start address" +"holly","014c","4","TA_YUV_TEX_CTRL","RW","YUV converter control" +"holly","0150","4","TA_YUV_TEX_CNT","R","YUV converter macro block counter value" +,,,,, +"holly","0160","4","TA_LIST_CONT","RW","TA continuation processing" +"holly","0164","4","TA_NEXT_OPB_INIT","RW","Additional OPB starting address" +,,,,, +"holly","0200","512","FOG_TABLE","RW","Look-up table fog data" +,,,,, +"holly","0600","2400","TA_OL_POINTERS","R","TA Object List Pointer data" +,,,,, +"holly","1000","4096","PALETTE_RAM","RW","Palette RAM" diff --git a/regs/holly.ods b/regs/holly.ods new file mode 100644 index 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zuWouqMB6|^?0=k_AOXa)_9A#EtlMAmem%Km!P{s4bqh6N#&}^*7ZR$#(X6@yA&6IN&dlk<1%7>S`xhwWYV-T2dtG0a_e;+OZl4Q&K76fgmd%1TYNGT} zb8u?m(5=bH?kA4PYJI9ny*k`9W$xZgTFdS)x%A%;3%^#V&d!YJsf)|ZP=4#&8?EzM zoi3lI>!4<{wtKAGnRfcTOVy9Bif~Y}MJJc8AFzGl?Q7)Yl3JNgIYrlbzR%}ir#M?^ z$vlS^m+^`xGWT&I CZah!` literal 0 HcmV?d00001 diff --git a/regs/sh7091.csv b/regs/sh7091.csv new file mode 100644 index 0000000..c5e7eae --- /dev/null +++ b/regs/sh7091.csv @@ -0,0 +1,126 @@ +"block","offset","address","size","name","r/w","description" +"CCN","00","0000",4,"PTEH","RW","Page table entry high register" +"CCN","00","0004",4,"PTEL","RW","Page table entry low register" +"CCN","00","0008",4,"TTB","RW","Translation table base register" +"CCN","00","000c",4,"TEA","RW","TLB exception address register" +"CCN","00","0010",4,"MMUCR","RW","MMU control register" +"CCN","00","0014",1,"BASRA","RW","Break ASID register A" +"CCN","00","0018",1,"BASRB","RW","Break ASID register B" +"CCN","00","001c",4,"CCR","RW","Cache control register" +"CCN","00","0020",4,"TRA","RW","TRAPA exception register" +"CCN","00","0024",4,"EXPEVT","RW","Exception event register" +"CCN","00","0028",4,"INTEVT","RW","Interrupt event register" +"CCN","00","0034",4,"PTEA","RW","Page table entry assistance register" +"CCN","00","0038",4,"QACR0","RW","Queue address control register 0" +"CCN","00","003c",4,"QACR1","RW","Queue address control register 1" +,,,,,, +"UBC","20","0000",4,"BARA","RW","Break address register A" +"UBC","20","0004",1,"BAMRA","RW","Break address mask register A" +"UBC","20","0008",2,"BBRA","RW","Break bus cycle register A" +"UBC","20","000c",4,"BARB","RW","Break address register B" +"UBC","20","0010",1,"BAMRB","RW","Break address mask register B" +"UBC","20","0014",2,"BBRB","RW","Break bus cycle register B" +"UBC","20","0018",4,"BDRB","RW","Break data register B" +"UBC","20","001c",4,"BDMRB","RW","Break data mask register B" +"UBC","20","0020",2,"BRCR","RW","Break control register" +,,,,,, +"BSC","80","0000",4,"BCR1","RW","Bus control register 1" +"BSC","80","0004",2,"BCR2","RW","Bus control register 2" +"BSC","80","0008",4,"WCR1","RW","Wait state control register 1" +"BSC","80","000c",4,"WCR2","RW","Wait state control register 2" +"BSC","80","0010",4,"WCR3","RW","Wait state control register 3" +"BSC","80","0014",4,"MCR","RW","Memory control register" +"BSC","80","0018",2,"PCR","RW","PCMCIA control register" +"BSC","80","001c",2,"RTCSR","RW","Refresh timer control/status register" +"BSC","80","0020",2,"RTCNT","RW","Refresh timer counter" +"BSC","80","0024",2,"RTCOR","RW","Refresh timer constant counter" +"BSC","80","0028",2,"RFCR","RW","Refresh count register" +"BSC","80","002c",4,"PCTRA","RW","Port control register A" +"BSC","80","0030",2,"PDTRA","RW","Port data register A" +"BSC","80","0040",4,"PCTRB","RW","Port control register B" +"BSC","80","0044",2,"PDTRB","RW","Port data register B" +"BSC","80","0048",2,"GPIOIC","RW","GPIO interrupt control register" +"BSC","90","0000",65536,"SDMR2","W","Synchronous DRAM mode registers" +"BSC","94","0000",65536,"SDMR3","W","Synchronous DRAM mode registers" +,,,,,, +"DMAC","a0","0000",4,"SAR0","RW","DMA source address register 0" +"DMAC","a0","0004",4,"DAR0","RW","DMA destination address register 0" +"DMAC","a0","0008",4,"DMATCR0","RW","DMA transfer count register 0" +"DMAC","a0","000c",4,"CHCR0","RW","DMA control register 0" +"DMAC","a0","0010",4,"SAR1","RW","DMA source address register 1" +"DMAC","a0","0014",4,"DAR1","RW","DMA destination address register 1" +"DMAC","a0","0018",4,"DMATCR1","RW","DMA transfer count register 1" +"DMAC","a0","001c",4,"CHCR1","RW","DMA control register 1" +"DMAC","a0","0020",4,"SAR2","RW","DMA source address register 2" +"DMAC","a0","0024",4,"DAR2","RW","DMA destination address register 2" +"DMAC","a0","0028",4,"DMATCR2","RW","DMA transfer count register 2" +"DMAC","a0","002c",4,"CHCR2","RW","DMA control register 2" +"DMAC","a0","0030",4,"SAR3","RW","DMA source address register 3" +"DMAC","a0","0034",4,"DAR3","RW","DMA destination address register 3" +"DMAC","a0","0038",4,"DMATCR3","RW","DMA transfer count register 3" +"DMAC","a0","003c",4,"CHCR3","RW","DMA control register 3" +"DMAC","a0","0040",4,"DMAOR","RW","DMA operation register" +,,,,,, +"CPG","c0","0000",2,"FRQCR","RW","Frequency control register" +"CPG","c0","0004",1,"STBCR","RW","Standby control register" +"CPG","c0","0008",2,"WTCNT","RW","Watchdog timer counter" +"CPG","c0","000c",2,"WTCSR","RW","Watchdog timer control/status register" +"CPG","c0","0010",1,"STBCR2","RW","Standby control register 2" +,,,,,, +"RTC","c8","0000",1,"R64CNT","R","64 Hz counter" +"RTC","c8","0004",1,"RSECCNT","RW","Second counter" +"RTC","c8","0008",1,"RMINCNT","RW","Minute counter" +"RTC","c8","000c",1,"RHRCNT","RW","Hour counter" +"RTC","c8","0010",1,"RWKCNT","RW","Day-of-week counter" +"RTC","c8","0014",1,"RDAYCNT","RW","Day counter" +"RTC","c8","0018",1,"RMONCNT","RW","Month counter" +"RTC","c8","001c",2,"RYRCNT","RW","Year counter" +"RTC","c8","0020",1,"RSECAR","RW","Second alarm register" +"RTC","c8","0024",1,"RMINAR","RW","Minute alarm register" +"RTC","c8","0028",1,"RHRAR","RW","Hour alarm register" +"RTC","c8","002c",1,"RWKAR","RW","Day-of-week alarm register" +"RTC","c8","0030",1,"RDAYAR","RW","Day alarm register" +"RTC","c8","0034",1,"RMONAR","RW","Month alarm register" +"RTC","c8","0038",1,"RCR1","RW","RTC control register 1" +"RTC","c8","003c",1,"RCR2","RW","RTC control register 2" +,,,,,, +"INTC","d0","0000",2,"ICR","RW","Interrupt control register" +"INTC","d0","0004",2,"IPRA","RW","Interrupt priority register A" +"INTC","d0","0008",2,"IPRB","RW","Interrupt priority register B" +"INTC","d0","000c",2,"IPRC","RW","Interrupt priority register C" +,,,,,, +"TMU","d8","0000",1,"TOCR","RW","Timer output control register" +"TMU","d8","0004",1,"TSTR","RW","Timer start register" +"TMU","d8","0008",4,"TCOR0","RW","Timer constant register 0" +"TMU","d8","000c",4,"TCNT0","RW","Timer counter 0" +"TMU","d8","0010",2,"TCR0","RW","Timer control register 0" +"TMU","d8","0014",4,"TCOR1","RW","Timer constant register 1" +"TMU","d8","0018",4,"TCNT1","RW","Timer counter 1" +"TMU","d8","001c",2,"TCR1","RW","Timer control register 1" +"TMU","d8","0020",4,"TCOR2","RW","Timer constant register 2" +"TMU","d8","0024",4,"TCNT2","RW","Timer counter 2" +"TMU","d8","0028",2,"TCR2","RW","Timer control register 2" +"TMU","d8","002c",4,"TCPR2","R","Timer input capture register 2" +,,,,,, +"SCI","e0","0000",1,"SCSMR1","RW","Serial mode register 1" +"SCI","e0","0004",1,"SCBRR1","RW","Bit rate register 1" +"SCI","e0","0008",1,"SCSCR1","RW","Serial control register 1" +"SCI","e0","000c",1,"SCTDR1","RW","Transmit data register 1" +"SCI","e0","0010",1,"SCSSR1","RW","Serial status register 1" +"SCI","e0","0014",1,"SCRDR1","R","Receive data register 1" +"SCI","e0","0018",1,"SCSCMR1","RW","Smart card mode register 1" +"SCI","e0","001c",1,"SCSPTR1","RW","Serial port register" +,,,,,, +"SCIF","e8","0000",2,"SCSMR2","RW","Serial mode register 2" +"SCIF","e8","0004",1,"SCBRR2","RW","Bit rate register 2" +"SCIF","e8","0008",2,"SCSCR2","RW","Serial control register 2" +"SCIF","e8","000c",1,"SCFTDR2","W","Transmit FIFO data register 2" +"SCIF","e8","0010",2,"SCFSR2","RW","Serial status register 2" +"SCIF","e8","0014",1,"SCFRDR2","R","Receive FIFO data register 2" +"SCIF","e8","0018",2,"SCFCR2","RW","FIFO control register" +"SCIF","e8","001c",2,"SCFDR2","R","FIFO data count register" +"SCIF","e8","0020",2,"SCSPTR2","RW","Serial port register 2" +"SCIF","e8","0024",2,"SCLSR2","RW","Line status register 2" +,,,,,, +"UDI","f0","0000",2,"SDIR","R","Instruction register" +"UDI","f0","0008",4,"SDDR","R","Data register" diff --git a/regs/sh7091.ods b/regs/sh7091.ods new file mode 100644 index 0000000000000000000000000000000000000000..34cb24c27ea9c531dea697efdc6d343185a6888c GIT binary patch literal 21788 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zR|$a%VOJ#O`>mf9i_6c@_R+*o+Rb@|)(@a}my(L^_FSP1UC3Af<3$HjU6_}KdMDL9 z82gpfFa*BsA;NV z){+oy+)4&VI8ZrVjQ2Aa;=VxiQ&v^03d4}GD5zNZIgi^Q}hwi$N@pqBCBur*akJlauE z5Lyvg>L6s%bk@Z$g^+WMHwgk}FN>sQ*V}-ZLsw2r4WZU3jZi5`=kSDfd{ZIyLRIj| zRSnplSZGj?Qr{1S+XL(_LBzpCfRrs^PA3#9PbQ(6<0u!mw&yb(?bo0nzxbre=Iqqq zQKKrzhnCilW;}4aRlxv|N0{-_Nj{-^rMd)#>xwpLkzUD%b`Am%p`m)Q6XUVhk8~C_ zzRiZW=7C@OqH4J>&Nk|}#41{P0jJL+OkZj~CA*2BIQYR=O%hfgwktlOqf71tx0jV$ zB_lfbgyTf-4=C}@u~B6!DjpTA;2NRw9L!ww;(=9c0&z+7PPC0l0zirC+j} z8o8!yxsTJdCf+X*1J+hW`0$t5Ca4oC`-@XUj$bsh8x>ttvVGv$oq0n^Li^~?GaA%iIh~Ji~Si|3Y*^VsS*=O?? z_$@J6!{2?j5QaOu{MwBoE57*MWjoSvXP-?<;Fj$F&F2@y;m%IKc9iiiPTP@(JNs-x z54Xg+tp2gGe;^QdHv4sXBD?-+_A3(ce@;L1pY6QAOx!Uas+GaMnCC0fOlFHvLw% +#include + +struct ccn_reg { + uint32_t PTEH; /* Page table entry high register */ + uint32_t PTEL; /* Page table entry low register */ + uint32_t TTB; /* Translation table base register */ + uint32_t TEA; /* TLB exception address register */ + uint32_t MMUCR; /* MMU control register */ + uint8_t BASRA; /* Break ASID register A */ + uint8_t _pad0[3]; + uint8_t BASRB; /* Break ASID register B */ + uint8_t _pad1[3]; + uint32_t CCR; /* Cache control register */ + uint32_t TRA; /* TRAPA exception register */ + uint32_t EXPEVT; /* Exception event register */ + uint32_t INTEVT; /* Interrupt event register */ + uint8_t _pad2[8]; + uint32_t PTEA; /* Page table entry assistance register */ + uint32_t QACR0; /* Queue address control register 0 */ + uint32_t QACR1; /* Queue address control register 1 */ +}; + +static_assert((offsetof (struct ccn_reg, PTEH)) == 0x0); +static_assert((offsetof (struct ccn_reg, PTEL)) == 0x4); +static_assert((offsetof (struct ccn_reg, TTB)) == 0x8); +static_assert((offsetof (struct ccn_reg, TEA)) == 0xc); +static_assert((offsetof (struct ccn_reg, MMUCR)) == 0x10); +static_assert((offsetof (struct ccn_reg, BASRA)) == 0x14); +static_assert((offsetof (struct ccn_reg, BASRB)) == 0x18); +static_assert((offsetof (struct ccn_reg, CCR)) == 0x1c); +static_assert((offsetof (struct ccn_reg, TRA)) == 0x20); +static_assert((offsetof (struct ccn_reg, EXPEVT)) == 0x24); +static_assert((offsetof (struct ccn_reg, INTEVT)) == 0x28); +static_assert((offsetof (struct ccn_reg, PTEA)) == 0x34); +static_assert((offsetof (struct ccn_reg, QACR0)) == 0x38); +static_assert((offsetof (struct ccn_reg, QACR1)) == 0x3c); + +struct ubc_reg { + uint32_t BARA; /* Break address register A */ + uint8_t BAMRA; /* Break address mask register A */ + uint8_t _pad0[3]; + uint16_t BBRA; /* Break bus cycle register A */ + uint8_t _pad1[2]; + uint32_t BARB; /* Break address register B */ + uint8_t BAMRB; /* Break address mask register B */ + uint8_t _pad2[3]; + uint16_t BBRB; /* Break bus cycle register B */ + uint8_t _pad3[2]; + uint32_t BDRB; /* Break data register B */ + uint32_t BDMRB; /* Break data mask register B */ + uint16_t BRCR; /* Break control register */ +}; + +static_assert((offsetof (struct ubc_reg, BARA)) == 0x0); +static_assert((offsetof (struct ubc_reg, BAMRA)) == 0x4); +static_assert((offsetof (struct ubc_reg, BBRA)) == 0x8); +static_assert((offsetof (struct ubc_reg, BARB)) == 0xc); +static_assert((offsetof (struct ubc_reg, BAMRB)) == 0x10); +static_assert((offsetof (struct ubc_reg, BBRB)) == 0x14); +static_assert((offsetof (struct ubc_reg, BDRB)) == 0x18); +static_assert((offsetof (struct ubc_reg, BDMRB)) == 0x1c); +static_assert((offsetof (struct ubc_reg, BRCR)) == 0x20); + +struct bsc_reg { + uint32_t BCR1; /* Bus control register 1 */ + uint16_t BCR2; /* Bus control register 2 */ + uint8_t _pad0[2]; + uint32_t WCR1; /* Wait state control register 1 */ + uint32_t WCR2; /* Wait state control register 2 */ + uint32_t WCR3; /* Wait state control register 3 */ + uint32_t MCR; /* Memory control register */ + uint16_t PCR; /* PCMCIA control register */ + uint8_t _pad1[2]; + uint16_t RTCSR; /* Refresh timer control/status register */ + uint8_t _pad2[2]; + uint16_t RTCNT; /* Refresh timer counter */ + uint8_t _pad3[2]; + uint16_t RTCOR; /* Refresh timer constant counter */ + uint8_t _pad4[2]; + uint16_t RFCR; /* Refresh count register */ + uint8_t _pad5[2]; + uint32_t PCTRA; /* Port control register A */ + uint16_t PDTRA; /* Port data register A */ + uint8_t _pad6[14]; + uint32_t PCTRB; /* Port control register B */ + uint16_t PDTRB; /* Port data register B */ + uint8_t _pad7[2]; + uint16_t GPIOIC; /* GPIO interrupt control register */ + uint8_t _pad8[1048502]; + uint8_t SDMR2[65536]; /* Synchronous DRAM mode registers */ + uint8_t _pad9[196608]; + uint8_t SDMR3[65536]; /* Synchronous DRAM mode registers */ +}; + +static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0); +static_assert((offsetof (struct bsc_reg, BCR2)) == 0x4); +static_assert((offsetof (struct bsc_reg, WCR1)) == 0x8); +static_assert((offsetof (struct bsc_reg, WCR2)) == 0xc); +static_assert((offsetof (struct bsc_reg, WCR3)) == 0x10); +static_assert((offsetof (struct bsc_reg, MCR)) == 0x14); +static_assert((offsetof (struct bsc_reg, PCR)) == 0x18); +static_assert((offsetof (struct bsc_reg, RTCSR)) == 0x1c); +static_assert((offsetof (struct bsc_reg, RTCNT)) == 0x20); +static_assert((offsetof (struct bsc_reg, RTCOR)) == 0x24); +static_assert((offsetof (struct bsc_reg, RFCR)) == 0x28); +static_assert((offsetof (struct bsc_reg, PCTRA)) == 0x2c); +static_assert((offsetof (struct bsc_reg, PDTRA)) == 0x30); +static_assert((offsetof (struct bsc_reg, PCTRB)) == 0x40); +static_assert((offsetof (struct bsc_reg, PDTRB)) == 0x44); +static_assert((offsetof (struct bsc_reg, GPIOIC)) == 0x48); +static_assert((offsetof (struct bsc_reg, SDMR2)) == 0x100000); +static_assert((offsetof (struct bsc_reg, SDMR3)) == 0x140000); + +struct dmac_reg { + uint32_t SAR0; /* DMA source address register 0 */ + uint32_t DAR0; /* DMA destination address register 0 */ + uint32_t DMATCR0; /* DMA transfer count register 0 */ + uint32_t CHCR0; /* DMA control register 0 */ + uint32_t SAR1; /* DMA source address register 1 */ + uint32_t DAR1; /* DMA destination address register 1 */ + uint32_t DMATCR1; /* DMA transfer count register 1 */ + uint32_t CHCR1; /* DMA control register 1 */ + uint32_t SAR2; /* DMA source address register 2 */ + uint32_t DAR2; /* DMA destination address register 2 */ + uint32_t DMATCR2; /* DMA transfer count register 2 */ + uint32_t CHCR2; /* DMA control register 2 */ + uint32_t SAR3; /* DMA source address register 3 */ + uint32_t DAR3; /* DMA destination address register 3 */ + uint32_t DMATCR3; /* DMA transfer count register 3 */ + uint32_t CHCR3; /* DMA control register 3 */ + uint32_t DMAOR; /* DMA operation register */ +}; + +static_assert((offsetof (struct dmac_reg, SAR0)) == 0x0); +static_assert((offsetof (struct dmac_reg, DAR0)) == 0x4); +static_assert((offsetof (struct dmac_reg, DMATCR0)) == 0x8); +static_assert((offsetof (struct dmac_reg, CHCR0)) == 0xc); +static_assert((offsetof (struct dmac_reg, SAR1)) == 0x10); +static_assert((offsetof (struct dmac_reg, DAR1)) == 0x14); +static_assert((offsetof (struct dmac_reg, DMATCR1)) == 0x18); +static_assert((offsetof (struct dmac_reg, CHCR1)) == 0x1c); +static_assert((offsetof (struct dmac_reg, SAR2)) == 0x20); +static_assert((offsetof (struct dmac_reg, DAR2)) == 0x24); +static_assert((offsetof (struct dmac_reg, DMATCR2)) == 0x28); +static_assert((offsetof (struct dmac_reg, CHCR2)) == 0x2c); +static_assert((offsetof (struct dmac_reg, SAR3)) == 0x30); +static_assert((offsetof (struct dmac_reg, DAR3)) == 0x34); +static_assert((offsetof (struct dmac_reg, DMATCR3)) == 0x38); +static_assert((offsetof (struct dmac_reg, CHCR3)) == 0x3c); +static_assert((offsetof (struct dmac_reg, DMAOR)) == 0x40); + +struct cpg_reg { + uint16_t FRQCR; /* Frequency control register */ + uint8_t _pad0[2]; + uint8_t STBCR; /* Standby control register */ + uint8_t _pad1[3]; + uint16_t WTCNT; /* Watchdog timer counter */ + uint8_t _pad2[2]; + uint16_t WTCSR; /* Watchdog timer control/status register */ + uint8_t _pad3[2]; + uint8_t STBCR2; /* Standby control register 2 */ +}; + +static_assert((offsetof (struct cpg_reg, FRQCR)) == 0x0); +static_assert((offsetof (struct cpg_reg, STBCR)) == 0x4); +static_assert((offsetof (struct cpg_reg, WTCNT)) == 0x8); +static_assert((offsetof (struct cpg_reg, WTCSR)) == 0xc); +static_assert((offsetof (struct cpg_reg, STBCR2)) == 0x10); + +struct rtc_reg { + uint8_t R64CNT; /* 64 Hz counter */ + uint8_t _pad0[3]; + uint8_t RSECCNT; /* Second counter */ + uint8_t _pad1[3]; + uint8_t RMINCNT; /* Minute counter */ + uint8_t _pad2[3]; + uint8_t RHRCNT; /* Hour counter */ + uint8_t _pad3[3]; + uint8_t RWKCNT; /* Day-of-week counter */ + uint8_t _pad4[3]; + uint8_t RDAYCNT; /* Day counter */ + uint8_t _pad5[3]; + uint8_t RMONCNT; /* Month counter */ + uint8_t _pad6[3]; + uint16_t RYRCNT; /* Year counter */ + uint8_t _pad7[2]; + uint8_t RSECAR; /* Second alarm register */ + uint8_t _pad8[3]; + uint8_t RMINAR; /* Minute alarm register */ + uint8_t _pad9[3]; + uint8_t RHRAR; /* Hour alarm register */ + uint8_t _pad10[3]; + uint8_t RWKAR; /* Day-of-week alarm register */ + uint8_t _pad11[3]; + uint8_t RDAYAR; /* Day alarm register */ + uint8_t _pad12[3]; + uint8_t RMONAR; /* Month alarm register */ + uint8_t _pad13[3]; + uint8_t RCR1; /* RTC control register 1 */ + uint8_t _pad14[3]; + uint8_t RCR2; /* RTC control register 2 */ +}; + +static_assert((offsetof (struct rtc_reg, R64CNT)) == 0x0); +static_assert((offsetof (struct rtc_reg, RSECCNT)) == 0x4); +static_assert((offsetof (struct rtc_reg, RMINCNT)) == 0x8); +static_assert((offsetof (struct rtc_reg, RHRCNT)) == 0xc); +static_assert((offsetof (struct rtc_reg, RWKCNT)) == 0x10); +static_assert((offsetof (struct rtc_reg, RDAYCNT)) == 0x14); +static_assert((offsetof (struct rtc_reg, RMONCNT)) == 0x18); +static_assert((offsetof (struct rtc_reg, RYRCNT)) == 0x1c); +static_assert((offsetof (struct rtc_reg, RSECAR)) == 0x20); +static_assert((offsetof (struct rtc_reg, RMINAR)) == 0x24); +static_assert((offsetof (struct rtc_reg, RHRAR)) == 0x28); +static_assert((offsetof (struct rtc_reg, RWKAR)) == 0x2c); +static_assert((offsetof (struct rtc_reg, RDAYAR)) == 0x30); +static_assert((offsetof (struct rtc_reg, RMONAR)) == 0x34); +static_assert((offsetof (struct rtc_reg, RCR1)) == 0x38); +static_assert((offsetof (struct rtc_reg, RCR2)) == 0x3c); + +struct intc_reg { + uint16_t ICR; /* Interrupt control register */ + uint8_t _pad0[2]; + uint16_t IPRA; /* Interrupt priority register A */ + uint8_t _pad1[2]; + uint16_t IPRB; /* Interrupt priority register B */ + uint8_t _pad2[2]; + uint16_t IPRC; /* Interrupt priority register C */ +}; + +static_assert((offsetof (struct intc_reg, ICR)) == 0x0); +static_assert((offsetof (struct intc_reg, IPRA)) == 0x4); +static_assert((offsetof (struct intc_reg, IPRB)) == 0x8); +static_assert((offsetof (struct intc_reg, IPRC)) == 0xc); + +struct tmu_reg { + uint8_t TOCR; /* Timer output control register */ + uint8_t _pad0[3]; + uint8_t TSTR; /* Timer start register */ + uint8_t _pad1[3]; + uint32_t TCOR0; /* Timer constant register 0 */ + uint32_t TCNT0; /* Timer counter 0 */ + uint16_t TCR0; /* Timer control register 0 */ + uint8_t _pad2[2]; + uint32_t TCOR1; /* Timer constant register 1 */ + uint32_t TCNT1; /* Timer counter 1 */ + uint16_t TCR1; /* Timer control register 1 */ + uint8_t _pad3[2]; + uint32_t TCOR2; /* Timer constant register 2 */ + uint32_t TCNT2; /* Timer counter 2 */ + uint16_t TCR2; /* Timer control register 2 */ + uint8_t _pad4[2]; + uint32_t TCPR2; /* Timer input capture register 2 */ +}; + +static_assert((offsetof (struct tmu_reg, TOCR)) == 0x0); +static_assert((offsetof (struct tmu_reg, TSTR)) == 0x4); +static_assert((offsetof (struct tmu_reg, TCOR0)) == 0x8); +static_assert((offsetof (struct tmu_reg, TCNT0)) == 0xc); +static_assert((offsetof (struct tmu_reg, TCR0)) == 0x10); +static_assert((offsetof (struct tmu_reg, TCOR1)) == 0x14); +static_assert((offsetof (struct tmu_reg, TCNT1)) == 0x18); +static_assert((offsetof (struct tmu_reg, TCR1)) == 0x1c); +static_assert((offsetof (struct tmu_reg, TCOR2)) == 0x20); +static_assert((offsetof (struct tmu_reg, TCNT2)) == 0x24); +static_assert((offsetof (struct tmu_reg, TCR2)) == 0x28); +static_assert((offsetof (struct tmu_reg, TCPR2)) == 0x2c); + +struct sci_reg { + uint8_t SCSMR1; /* Serial mode register 1 */ + uint8_t _pad0[3]; + uint8_t SCBRR1; /* Bit rate register 1 */ + uint8_t _pad1[3]; + uint8_t SCSCR1; /* Serial control register 1 */ + uint8_t _pad2[3]; + uint8_t SCTDR1; /* Transmit data register 1 */ + uint8_t _pad3[3]; + uint8_t SCSSR1; /* Serial status register 1 */ + uint8_t _pad4[3]; + uint8_t SCRDR1; /* Receive data register 1 */ + uint8_t _pad5[3]; + uint8_t SCSCMR1; /* Smart card mode register 1 */ + uint8_t _pad6[3]; + uint8_t SCSPTR1; /* Serial port register */ +}; + +static_assert((offsetof (struct sci_reg, SCSMR1)) == 0x0); +static_assert((offsetof (struct sci_reg, SCBRR1)) == 0x4); +static_assert((offsetof (struct sci_reg, SCSCR1)) == 0x8); +static_assert((offsetof (struct sci_reg, SCTDR1)) == 0xc); +static_assert((offsetof (struct sci_reg, SCSSR1)) == 0x10); +static_assert((offsetof (struct sci_reg, SCRDR1)) == 0x14); +static_assert((offsetof (struct sci_reg, SCSCMR1)) == 0x18); +static_assert((offsetof (struct sci_reg, SCSPTR1)) == 0x1c); + +struct scif_reg { + uint16_t SCSMR2; /* Serial mode register 2 */ + uint8_t _pad0[2]; + uint8_t SCBRR2; /* Bit rate register 2 */ + uint8_t _pad1[3]; + uint16_t SCSCR2; /* Serial control register 2 */ + uint8_t _pad2[2]; + uint8_t SCFTDR2; /* Transmit FIFO data register 2 */ + uint8_t _pad3[3]; + uint16_t SCFSR2; /* Serial status register 2 */ + uint8_t _pad4[2]; + uint8_t SCFRDR2; /* Receive FIFO data register 2 */ + uint8_t _pad5[3]; + uint16_t SCFCR2; /* FIFO control register */ + uint8_t _pad6[2]; + uint16_t SCFDR2; /* FIFO data count register */ + uint8_t _pad7[2]; + uint16_t SCSPTR2; /* Serial port register 2 */ + uint8_t _pad8[2]; + uint16_t SCLSR2; /* Line status register 2 */ +}; + +static_assert((offsetof (struct scif_reg, SCSMR2)) == 0x0); +static_assert((offsetof (struct scif_reg, SCBRR2)) == 0x4); +static_assert((offsetof (struct scif_reg, SCSCR2)) == 0x8); +static_assert((offsetof (struct scif_reg, SCFTDR2)) == 0xc); +static_assert((offsetof (struct scif_reg, SCFSR2)) == 0x10); +static_assert((offsetof (struct scif_reg, SCFRDR2)) == 0x14); +static_assert((offsetof (struct scif_reg, SCFCR2)) == 0x18); +static_assert((offsetof (struct scif_reg, SCFDR2)) == 0x1c); +static_assert((offsetof (struct scif_reg, SCSPTR2)) == 0x20); +static_assert((offsetof (struct scif_reg, SCLSR2)) == 0x24); + +struct udi_reg { + uint16_t SDIR; /* Instruction register */ + uint8_t _pad0[6]; + uint32_t SDDR; /* Data register */ +}; + +static_assert((offsetof (struct udi_reg, SDIR)) == 0x0); +static_assert((offsetof (struct udi_reg, SDDR)) == 0x8); + +struct sh7091_reg { + ccn_reg CCN; + uint8_t _pad0[0x200000 - (sizeof (struct ccn_reg))]; + ubc_reg UBC; + uint8_t _pad1[0x600000 - (sizeof (struct ubc_reg))]; + bsc_reg BSC; + uint8_t _pad2[0x200000 - (sizeof (struct bsc_reg))]; + dmac_reg DMAC; + uint8_t _pad3[0x200000 - (sizeof (struct dmac_reg))]; + cpg_reg CPG; + uint8_t _pad4[0x80000 - (sizeof (struct cpg_reg))]; + rtc_reg RTC; + uint8_t _pad5[0x80000 - (sizeof (struct rtc_reg))]; + intc_reg INTC; + uint8_t _pad6[0x80000 - (sizeof (struct intc_reg))]; + tmu_reg TMU; + uint8_t _pad7[0x80000 - (sizeof (struct tmu_reg))]; + sci_reg SCI; + uint8_t _pad8[0x80000 - (sizeof (struct sci_reg))]; + scif_reg SCIF; + uint8_t _pad9[0x80000 - (sizeof (struct scif_reg))]; + udi_reg UDI; +}; + +static_assert((offsetof (struct sh7091_reg, CCN)) == 0x0); +static_assert((offsetof (struct sh7091_reg, UBC)) == 0x200000); +static_assert((offsetof (struct sh7091_reg, BSC)) == 0x800000); +static_assert((offsetof (struct sh7091_reg, DMAC)) == 0xa00000); +static_assert((offsetof (struct sh7091_reg, CPG)) == 0xc00000); +static_assert((offsetof (struct sh7091_reg, RTC)) == 0xc80000); +static_assert((offsetof (struct sh7091_reg, INTC)) == 0xd00000); +static_assert((offsetof (struct sh7091_reg, TMU)) == 0xd80000); +static_assert((offsetof (struct sh7091_reg, SCI)) == 0xe00000); +static_assert((offsetof (struct sh7091_reg, SCIF)) == 0xe80000); +static_assert((offsetof (struct sh7091_reg, UDI)) == 0xf00000); + +extern sh7091_reg SH7091; + diff --git a/type.h b/type.h new file mode 100644 index 0000000..bc79def --- /dev/null +++ b/type.h @@ -0,0 +1,16 @@ +#include +#include + +#ifndef __cplusplus +#ifndef static_assert +#define static_assert _Static_assert +#endif +#endif + +typedef volatile uint8_t reg8; +typedef volatile uint16_t reg16; +typedef volatile uint32_t reg32; + +static_assert((sizeof (reg8)) == 1); +static_assert((sizeof (reg16)) == 2); +static_assert((sizeof (reg32)) == 4);