diff --git a/aica.hpp b/aica.hpp
deleted file mode 100644
index 64b856f..0000000
--- a/aica.hpp
+++ /dev/null
@@ -1 +0,0 @@
-extern reg32 aica[0x8000] __asm("aica");
diff --git a/aica/aica.hpp b/aica/aica.hpp
new file mode 100644
index 0000000..9704c89
--- /dev/null
+++ b/aica/aica.hpp
@@ -0,0 +1,31 @@
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+#include "aica_channel.hpp"
+#include "aica_dsp_out.hpp"
+#include "aica_common.hpp"
+#include "aica_rtc.hpp"
+
+struct aica_reg {
+  // 0x00700000 [64] channel data start
+  // 0x00702000 [64] channel data end
+  // 0x00702000 [18] dsp out start
+  // 0x00702048 [18] dsp out end
+  // padding 0x7b8
+  // 0x00702800 common data start
+
+  struct aica_channel channel[64];
+  struct aica_dsp_out dsp_out[18];
+  const uint16_t _pad[0x7b8 / 2];
+  struct aica_common common;
+};
+
+static_assert((sizeof (struct aica_reg)) == 0x2d08);
+static_assert((offsetof (struct aica_reg, channel)) == 0);
+static_assert((offsetof (struct aica_reg, dsp_out)) == 0x2000);
+static_assert((offsetof (struct aica_reg, common)) == 0x2800);
+
+extern struct aica_reg aica __asm("aica");
+extern struct aica_rtc aica_rtc __asm("aica_rtc");
diff --git a/aica/aica_channel.hpp b/aica/aica_channel.hpp
new file mode 100644
index 0000000..5b2e4f0
--- /dev/null
+++ b/aica/aica_channel.hpp
@@ -0,0 +1,426 @@
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+struct aica_channel {
+  reg16 reg_0000;
+  const reg16 _pad0[1];
+  reg16 reg_0004;
+  const reg16 _pad1[1];
+  reg16 reg_0008;
+  const reg16 _pad2[1];
+  reg16 reg_000c;
+  const reg16 _pad3[1];
+  reg16 reg_0010;
+  const reg16 _pad4[1];
+  reg16 reg_0014;
+  const reg16 _pad5[1];
+  reg16 reg_0018;
+  const reg16 _pad6[1];
+  reg16 reg_001c;
+  const reg16 _pad7[1];
+  reg16 reg_0020;
+  const reg16 _pad8[1];
+  reg16 reg_0024;
+  const reg16 _pad9[1];
+  reg16 reg_0028;
+  const reg16 _pad10[1];
+  reg16 reg_002c;
+  const reg16 _pad11[1];
+  reg16 reg_0030;
+  const reg16 _pad12[1];
+  reg16 reg_0034;
+  const reg16 _pad13[1];
+  reg16 reg_0038;
+  const reg16 _pad14[1];
+  reg16 reg_003c;
+  const reg16 _pad15[1];
+  reg16 reg_0040;
+  const reg16 _pad16[1];
+  reg16 reg_0044;
+  const reg16 _pad17[1];
+  const reg16 _pad18[28];
+
+  uint32_t KYONEX() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 15) & 0x1) << 0);
+  }
+  void KYONEX(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x1) << 15) | (reg_0000 & 0x7fff);
+  }
+
+  uint32_t KYONB() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 14) & 0x1) << 0);
+  }
+  void KYONB(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x1) << 14) | (reg_0000 & 0xbfff);
+  }
+
+  uint32_t SSCTL() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 10) & 0x1) << 0);
+  }
+  void SSCTL(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x1) << 10) | (reg_0000 & 0xfbff);
+  }
+
+  uint32_t LPCTL() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 9) & 0x1) << 0);
+  }
+  void LPCTL(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x1) << 9) | (reg_0000 & 0xfdff);
+  }
+
+  uint32_t PCMS() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 7) & 0x3) << 0);
+  }
+  void PCMS(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x3) << 7) | (reg_0000 & 0xfe7f);
+  }
+
+  uint32_t SA() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 0) & 0x7f) << 16) | (static_cast<uint32_t>((reg_0004 >> 0) & 0xffff) << 0);
+  }
+  void SA(const uint32_t v)
+  {
+    reg_0000 = (((v >> 16) & 0x7f) << 0) | (reg_0000 & 0xff80);
+    reg_0004 = (((v >> 0) & 0xffff) << 0);
+  }
+
+  uint32_t LSA() const
+  {
+    return (static_cast<uint32_t>((reg_0008 >> 0) & 0xffff) << 0);
+  }
+  void LSA(const uint32_t v)
+  {
+    reg_0008 = (((v >> 0) & 0xffff) << 0);
+  }
+
+  uint32_t LEA() const
+  {
+    return (static_cast<uint32_t>((reg_000c >> 0) & 0xffff) << 0);
+  }
+  void LEA(const uint32_t v)
+  {
+    reg_000c = (((v >> 0) & 0xffff) << 0);
+  }
+
+  uint32_t D2R() const
+  {
+    return (static_cast<uint32_t>((reg_0010 >> 11) & 0x1f) << 0);
+  }
+  void D2R(const uint32_t v)
+  {
+    reg_0010 = (((v >> 0) & 0x1f) << 11) | (reg_0010 & 0x7ff);
+  }
+
+  uint32_t D1R() const
+  {
+    return (static_cast<uint32_t>((reg_0010 >> 6) & 0x1f) << 0);
+  }
+  void D1R(const uint32_t v)
+  {
+    reg_0010 = (((v >> 0) & 0x1f) << 6) | (reg_0010 & 0xf83f);
+  }
+
+  uint32_t AR() const
+  {
+    return (static_cast<uint32_t>((reg_0010 >> 0) & 0x1f) << 0);
+  }
+  void AR(const uint32_t v)
+  {
+    reg_0010 = (((v >> 0) & 0x1f) << 0) | (reg_0010 & 0xffe0);
+  }
+
+  uint32_t LPSLNK() const
+  {
+    return (static_cast<uint32_t>((reg_0014 >> 14) & 0x1) << 0);
+  }
+  void LPSLNK(const uint32_t v)
+  {
+    reg_0014 = (((v >> 0) & 0x1) << 14) | (reg_0014 & 0xbfff);
+  }
+
+  uint32_t KRS() const
+  {
+    return (static_cast<uint32_t>((reg_0014 >> 10) & 0xf) << 0);
+  }
+  void KRS(const uint32_t v)
+  {
+    reg_0014 = (((v >> 0) & 0xf) << 10) | (reg_0014 & 0xc3ff);
+  }
+
+  uint32_t DL() const
+  {
+    return (static_cast<uint32_t>((reg_0014 >> 5) & 0x1f) << 0);
+  }
+  void DL(const uint32_t v)
+  {
+    reg_0014 = (((v >> 0) & 0x1f) << 5) | (reg_0014 & 0xfc1f);
+  }
+
+  uint32_t RR() const
+  {
+    return (static_cast<uint32_t>((reg_0014 >> 0) & 0x1f) << 0);
+  }
+  void RR(const uint32_t v)
+  {
+    reg_0014 = (((v >> 0) & 0x1f) << 0) | (reg_0014 & 0xffe0);
+  }
+
+  uint32_t OCT() const
+  {
+    return (static_cast<uint32_t>((reg_0018 >> 11) & 0xf) << 0);
+  }
+  void OCT(const uint32_t v)
+  {
+    reg_0018 = (((v >> 0) & 0xf) << 11) | (reg_0018 & 0x87ff);
+  }
+
+  uint32_t FNS() const
+  {
+    return (static_cast<uint32_t>((reg_0018 >> 0) & 0x3ff) << 0);
+  }
+  void FNS(const uint32_t v)
+  {
+    reg_0018 = (((v >> 0) & 0x3ff) << 0) | (reg_0018 & 0xfc00);
+  }
+
+  uint32_t LFORE() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 15) & 0x1) << 0);
+  }
+  void LFORE(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x1) << 15) | (reg_001c & 0x7fff);
+  }
+
+  uint32_t LFOF() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 10) & 0x1f) << 0);
+  }
+  void LFOF(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x1f) << 10) | (reg_001c & 0x83ff);
+  }
+
+  uint32_t PLFOWS() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 8) & 0x3) << 0);
+  }
+  void PLFOWS(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x3) << 8) | (reg_001c & 0xfcff);
+  }
+
+  uint32_t PLFOS() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 5) & 0x7) << 0);
+  }
+  void PLFOS(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x7) << 5) | (reg_001c & 0xff1f);
+  }
+
+  uint32_t ALFOWS() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 3) & 0x3) << 0);
+  }
+  void ALFOWS(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x3) << 3) | (reg_001c & 0xffe7);
+  }
+
+  uint32_t ALFOS() const
+  {
+    return (static_cast<uint32_t>((reg_001c >> 0) & 0x7) << 0);
+  }
+  void ALFOS(const uint32_t v)
+  {
+    reg_001c = (((v >> 0) & 0x7) << 0) | (reg_001c & 0xfff8);
+  }
+
+  uint32_t IMXL() const
+  {
+    return (static_cast<uint32_t>((reg_0020 >> 4) & 0xf) << 0);
+  }
+  void IMXL(const uint32_t v)
+  {
+    reg_0020 = (((v >> 0) & 0xf) << 4) | (reg_0020 & 0xff0f);
+  }
+
+  uint32_t ISEL() const
+  {
+    return (static_cast<uint32_t>((reg_0020 >> 0) & 0xf) << 0);
+  }
+  void ISEL(const uint32_t v)
+  {
+    reg_0020 = (((v >> 0) & 0xf) << 0) | (reg_0020 & 0xfff0);
+  }
+
+  uint32_t DISDL() const
+  {
+    return (static_cast<uint32_t>((reg_0024 >> 8) & 0xf) << 0);
+  }
+  void DISDL(const uint32_t v)
+  {
+    reg_0024 = (((v >> 0) & 0xf) << 8) | (reg_0024 & 0xf0ff);
+  }
+
+  uint32_t DIPAN() const
+  {
+    return (static_cast<uint32_t>((reg_0024 >> 0) & 0x1f) << 0);
+  }
+  void DIPAN(const uint32_t v)
+  {
+    reg_0024 = (((v >> 0) & 0x1f) << 0) | (reg_0024 & 0xffe0);
+  }
+
+  uint32_t TL() const
+  {
+    return (static_cast<uint32_t>((reg_0028 >> 8) & 0xff) << 0);
+  }
+  void TL(const uint32_t v)
+  {
+    reg_0028 = (((v >> 0) & 0xff) << 8) | (reg_0028 & 0xff);
+  }
+
+  uint32_t VOFF() const
+  {
+    return (static_cast<uint32_t>((reg_0028 >> 6) & 0x1) << 0);
+  }
+  void VOFF(const uint32_t v)
+  {
+    reg_0028 = (((v >> 0) & 0x1) << 6) | (reg_0028 & 0xffbf);
+  }
+
+  uint32_t LPOFF() const
+  {
+    return (static_cast<uint32_t>((reg_0028 >> 5) & 0x1) << 0);
+  }
+  void LPOFF(const uint32_t v)
+  {
+    reg_0028 = (((v >> 0) & 0x1) << 5) | (reg_0028 & 0xffdf);
+  }
+
+  uint32_t Q() const
+  {
+    return (static_cast<uint32_t>((reg_0028 >> 0) & 0x1f) << 0);
+  }
+  void Q(const uint32_t v)
+  {
+    reg_0028 = (((v >> 0) & 0x1f) << 0) | (reg_0028 & 0xffe0);
+  }
+
+  uint32_t FLV0() const
+  {
+    return (static_cast<uint32_t>((reg_002c >> 0) & 0x1fff) << 0);
+  }
+  void FLV0(const uint32_t v)
+  {
+    reg_002c = (((v >> 0) & 0x1fff) << 0);
+  }
+
+  uint32_t FLV1() const
+  {
+    return (static_cast<uint32_t>((reg_0030 >> 0) & 0x1fff) << 0);
+  }
+  void FLV1(const uint32_t v)
+  {
+    reg_0030 = (((v >> 0) & 0x1fff) << 0);
+  }
+
+  uint32_t FLV2() const
+  {
+    return (static_cast<uint32_t>((reg_0034 >> 0) & 0x1fff) << 0);
+  }
+  void FLV2(const uint32_t v)
+  {
+    reg_0034 = (((v >> 0) & 0x1fff) << 0);
+  }
+
+  uint32_t FLV3() const
+  {
+    return (static_cast<uint32_t>((reg_0038 >> 0) & 0x1fff) << 0);
+  }
+  void FLV3(const uint32_t v)
+  {
+    reg_0038 = (((v >> 0) & 0x1fff) << 0);
+  }
+
+  uint32_t FLV4() const
+  {
+    return (static_cast<uint32_t>((reg_003c >> 0) & 0x1fff) << 0);
+  }
+  void FLV4(const uint32_t v)
+  {
+    reg_003c = (((v >> 0) & 0x1fff) << 0);
+  }
+
+  uint32_t FAR() const
+  {
+    return (static_cast<uint32_t>((reg_0040 >> 8) & 0x1f) << 0);
+  }
+  void FAR(const uint32_t v)
+  {
+    reg_0040 = (((v >> 0) & 0x1f) << 8) | (reg_0040 & 0xe0ff);
+  }
+
+  uint32_t FD1R() const
+  {
+    return (static_cast<uint32_t>((reg_0040 >> 0) & 0x1f) << 0);
+  }
+  void FD1R(const uint32_t v)
+  {
+    reg_0040 = (((v >> 0) & 0x1f) << 0) | (reg_0040 & 0xffe0);
+  }
+
+  uint32_t FD2R() const
+  {
+    return (static_cast<uint32_t>((reg_0044 >> 8) & 0x1f) << 0);
+  }
+  void FD2R(const uint32_t v)
+  {
+    reg_0044 = (((v >> 0) & 0x1f) << 8) | (reg_0044 & 0xe0ff);
+  }
+
+  uint32_t FRR() const
+  {
+    return (static_cast<uint32_t>((reg_0044 >> 0) & 0x1f) << 0);
+  }
+  void FRR(const uint32_t v)
+  {
+    reg_0044 = (((v >> 0) & 0x1f) << 0) | (reg_0044 & 0xffe0);
+  }
+
+};
+
+static_assert((sizeof (aica_channel)) == 0x80 - 0x0);
+static_assert((offsetof (aica_channel, reg_0000)) == 0x0 - 0x0);
+static_assert((offsetof (aica_channel, reg_0004)) == 0x4 - 0x0);
+static_assert((offsetof (aica_channel, reg_0008)) == 0x8 - 0x0);
+static_assert((offsetof (aica_channel, reg_000c)) == 0xc - 0x0);
+static_assert((offsetof (aica_channel, reg_0010)) == 0x10 - 0x0);
+static_assert((offsetof (aica_channel, reg_0014)) == 0x14 - 0x0);
+static_assert((offsetof (aica_channel, reg_0018)) == 0x18 - 0x0);
+static_assert((offsetof (aica_channel, reg_001c)) == 0x1c - 0x0);
+static_assert((offsetof (aica_channel, reg_0020)) == 0x20 - 0x0);
+static_assert((offsetof (aica_channel, reg_0024)) == 0x24 - 0x0);
+static_assert((offsetof (aica_channel, reg_0028)) == 0x28 - 0x0);
+static_assert((offsetof (aica_channel, reg_002c)) == 0x2c - 0x0);
+static_assert((offsetof (aica_channel, reg_0030)) == 0x30 - 0x0);
+static_assert((offsetof (aica_channel, reg_0034)) == 0x34 - 0x0);
+static_assert((offsetof (aica_channel, reg_0038)) == 0x38 - 0x0);
+static_assert((offsetof (aica_channel, reg_003c)) == 0x3c - 0x0);
+static_assert((offsetof (aica_channel, reg_0040)) == 0x40 - 0x0);
+static_assert((offsetof (aica_channel, reg_0044)) == 0x44 - 0x0);
diff --git a/aica/aica_common.hpp b/aica/aica_common.hpp
new file mode 100644
index 0000000..c4a0508
--- /dev/null
+++ b/aica/aica_common.hpp
@@ -0,0 +1,665 @@
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+struct aica_common {
+  reg16 reg_2800;
+  const reg16 _pad0[1];
+  reg16 reg_2804;
+  const reg16 _pad1[1];
+  reg16 reg_2808;
+  const reg16 _pad2[1];
+  reg16 reg_280c;
+  const reg16 _pad3[1];
+  reg16 reg_2810;
+  const reg16 _pad4[1];
+  reg16 reg_2814;
+  const reg16 _pad5[1];
+  const reg16 _pad6[52];
+  reg16 reg_2880;
+  const reg16 _pad7[1];
+  reg16 reg_2884;
+  const reg16 _pad8[1];
+  reg16 reg_2888;
+  const reg16 _pad9[1];
+  reg16 reg_288c;
+  const reg16 _pad10[1];
+  reg16 reg_2890;
+  const reg16 _pad11[1];
+  reg16 reg_2894;
+  const reg16 _pad12[1];
+  reg16 reg_2898;
+  const reg16 _pad13[1];
+  reg16 reg_289c;
+  const reg16 _pad14[1];
+  reg16 reg_28a0;
+  const reg16 _pad15[1];
+  reg16 reg_28a4;
+  const reg16 _pad16[1];
+  reg16 reg_28a8;
+  const reg16 _pad17[1];
+  reg16 reg_28ac;
+  const reg16 _pad18[1];
+  reg16 reg_28b0;
+  const reg16 _pad19[1];
+  reg16 reg_28b4;
+  const reg16 _pad20[1];
+  reg16 reg_28b8;
+  const reg16 _pad21[1];
+  reg16 reg_28bc;
+  const reg16 _pad22[1];
+  const reg16 _pad23[416];
+  reg16 reg_2c00;
+  const reg16 _pad24[1];
+  const reg16 _pad25[126];
+  reg16 reg_2d00;
+  const reg16 _pad26[1];
+  reg16 reg_2d04;
+  const reg16 _pad27[1];
+
+  uint32_t MONO() const
+  {
+    return (static_cast<uint32_t>((reg_2800 >> 15) & 0x1) << 0);
+  }
+  void MONO(const uint32_t v)
+  {
+    reg_2800 = (((v >> 0) & 0x1) << 15) | (reg_2800 & 0x7fff);
+  }
+
+  uint32_t MEM8MB() const
+  {
+    return (static_cast<uint32_t>((reg_2800 >> 9) & 0x1) << 0);
+  }
+  void MEM8MB(const uint32_t v)
+  {
+    reg_2800 = (((v >> 0) & 0x1) << 9) | (reg_2800 & 0xfdff);
+  }
+
+  uint32_t DAC18B() const
+  {
+    return (static_cast<uint32_t>((reg_2800 >> 8) & 0x1) << 0);
+  }
+  void DAC18B(const uint32_t v)
+  {
+    reg_2800 = (((v >> 0) & 0x1) << 8) | (reg_2800 & 0xfeff);
+  }
+
+  uint32_t VER() const
+  {
+    return (static_cast<uint32_t>((reg_2800 >> 4) & 0xf) << 0);
+  }
+  void VER(const uint32_t v)
+  {
+    reg_2800 = (((v >> 0) & 0xf) << 4) | (reg_2800 & 0xff0f);
+  }
+
+  uint32_t MVOL() const
+  {
+    return (static_cast<uint32_t>((reg_2800 >> 0) & 0xf) << 0);
+  }
+  void MVOL(const uint32_t v)
+  {
+    reg_2800 = (((v >> 0) & 0xf) << 0) | (reg_2800 & 0xfff0);
+  }
+
+  uint32_t TESTB0() const
+  {
+    return (static_cast<uint32_t>((reg_2804 >> 15) & 0x1) << 0);
+  }
+  void TESTB0(const uint32_t v)
+  {
+    reg_2804 = (((v >> 0) & 0x1) << 15) | (reg_2804 & 0x7fff);
+  }
+
+  uint32_t RBL() const
+  {
+    return (static_cast<uint32_t>((reg_2804 >> 13) & 0x3) << 0);
+  }
+  void RBL(const uint32_t v)
+  {
+    reg_2804 = (((v >> 0) & 0x3) << 13) | (reg_2804 & 0x9fff);
+  }
+
+  uint32_t RBP() const
+  {
+    return (static_cast<uint32_t>((reg_2804 >> 0) & 0xfff) << 11);
+  }
+  void RBP(const uint32_t v)
+  {
+    reg_2804 = (((v >> 11) & 0xfff) << 0) | (reg_2804 & 0xf000);
+  }
+
+  uint32_t MOFUL() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 12) & 0x1) << 0);
+  }
+  void MOFUL(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0x1) << 12) | (reg_2808 & 0xefff);
+  }
+
+  uint32_t MOEMP() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 11) & 0x1) << 0);
+  }
+  void MOEMP(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0x1) << 11) | (reg_2808 & 0xf7ff);
+  }
+
+  uint32_t MIOVF() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 10) & 0x1) << 0);
+  }
+  void MIOVF(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0x1) << 10) | (reg_2808 & 0xfbff);
+  }
+
+  uint32_t MIFUL() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 9) & 0x1) << 0);
+  }
+  void MIFUL(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0x1) << 9) | (reg_2808 & 0xfdff);
+  }
+
+  uint32_t MIEMP() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 8) & 0x1) << 0);
+  }
+  void MIEMP(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0x1) << 8) | (reg_2808 & 0xfeff);
+  }
+
+  uint32_t MIBUF() const
+  {
+    return (static_cast<uint32_t>((reg_2808 >> 0) & 0xff) << 0);
+  }
+  void MIBUF(const uint32_t v)
+  {
+    reg_2808 = (((v >> 0) & 0xff) << 0) | (reg_2808 & 0xff00);
+  }
+
+  uint32_t AFSET() const
+  {
+    return (static_cast<uint32_t>((reg_280c >> 14) & 0x1) << 0);
+  }
+  void AFSET(const uint32_t v)
+  {
+    reg_280c = (((v >> 0) & 0x1) << 14) | (reg_280c & 0xbfff);
+  }
+
+  uint32_t MSLC() const
+  {
+    return (static_cast<uint32_t>((reg_280c >> 8) & 0x3f) << 0);
+  }
+  void MSLC(const uint32_t v)
+  {
+    reg_280c = (((v >> 0) & 0x3f) << 8) | (reg_280c & 0xc0ff);
+  }
+
+  uint32_t MOBUF() const
+  {
+    return (static_cast<uint32_t>((reg_280c >> 0) & 0xff) << 0);
+  }
+  void MOBUF(const uint32_t v)
+  {
+    reg_280c = (((v >> 0) & 0xff) << 0) | (reg_280c & 0xff00);
+  }
+
+  uint32_t LP() const
+  {
+    return (static_cast<uint32_t>((reg_2810 >> 15) & 0x1) << 0);
+  }
+  void LP(const uint32_t v)
+  {
+    reg_2810 = (((v >> 0) & 0x1) << 15) | (reg_2810 & 0x7fff);
+  }
+
+  uint32_t SGC() const
+  {
+    return (static_cast<uint32_t>((reg_2810 >> 14) & 0x1) << 0);
+  }
+  void SGC(const uint32_t v)
+  {
+    reg_2810 = (((v >> 0) & 0x1) << 14) | (reg_2810 & 0xbfff);
+  }
+
+  uint32_t EG() const
+  {
+    return (static_cast<uint32_t>((reg_2810 >> 0) & 0x1fff) << 0);
+  }
+  void EG(const uint32_t v)
+  {
+    reg_2810 = (((v >> 0) & 0x1fff) << 0) | (reg_2810 & 0xe000);
+  }
+
+  uint32_t CA() const
+  {
+    return (static_cast<uint32_t>((reg_2814 >> 0) & 0xffff) << 0);
+  }
+  void CA(const uint32_t v)
+  {
+    reg_2814 = (((v >> 0) & 0xffff) << 0);
+  }
+
+  uint32_t DMEA() const
+  {
+    return (static_cast<uint32_t>((reg_2880 >> 9) & 0x7f) << 16) | (static_cast<uint32_t>((reg_2884 >> 2) & 0x3fff) << 2);
+  }
+  void DMEA(const uint32_t v)
+  {
+    reg_2880 = (((v >> 16) & 0x7f) << 9) | (reg_2880 & 0x1ff);
+    reg_2884 = (((v >> 2) & 0x3fff) << 2);
+  }
+
+  uint32_t TSCD() const
+  {
+    return (static_cast<uint32_t>((reg_2880 >> 5) & 0x7) << 0);
+  }
+  void TSCD(const uint32_t v)
+  {
+    reg_2880 = (((v >> 0) & 0x7) << 5) | (reg_2880 & 0xff1f);
+  }
+
+  uint32_t T() const
+  {
+    return (static_cast<uint32_t>((reg_2880 >> 4) & 0x1) << 0);
+  }
+  void T(const uint32_t v)
+  {
+    reg_2880 = (((v >> 0) & 0x1) << 4) | (reg_2880 & 0xffef);
+  }
+
+  uint32_t MRWINH() const
+  {
+    return (static_cast<uint32_t>((reg_2880 >> 0) & 0xf) << 0);
+  }
+  void MRWINH(const uint32_t v)
+  {
+    reg_2880 = (((v >> 0) & 0xf) << 0) | (reg_2880 & 0xfff0);
+  }
+
+  uint32_t DGATE() const
+  {
+    return (static_cast<uint32_t>((reg_2888 >> 15) & 0x1) << 0);
+  }
+  void DGATE(const uint32_t v)
+  {
+    reg_2888 = (((v >> 0) & 0x1) << 15) | (reg_2888 & 0x7fff);
+  }
+
+  uint32_t DRGA() const
+  {
+    return (static_cast<uint32_t>((reg_2888 >> 2) & 0x1fff) << 2);
+  }
+  void DRGA(const uint32_t v)
+  {
+    reg_2888 = (((v >> 2) & 0x1fff) << 2) | (reg_2888 & 0x8003);
+  }
+
+  uint32_t DDIR() const
+  {
+    return (static_cast<uint32_t>((reg_288c >> 15) & 0x1) << 0);
+  }
+  void DDIR(const uint32_t v)
+  {
+    reg_288c = (((v >> 0) & 0x1) << 15) | (reg_288c & 0x7fff);
+  }
+
+  uint32_t DLG() const
+  {
+    return (static_cast<uint32_t>((reg_288c >> 2) & 0x1fff) << 2);
+  }
+  void DLG(const uint32_t v)
+  {
+    reg_288c = (((v >> 2) & 0x1fff) << 2) | (reg_288c & 0x8003);
+  }
+
+  uint32_t DEXE() const
+  {
+    return (static_cast<uint32_t>((reg_288c >> 0) & 0x1) << 0);
+  }
+  void DEXE(const uint32_t v)
+  {
+    reg_288c = (((v >> 0) & 0x1) << 0) | (reg_288c & 0xfffe);
+  }
+
+  uint32_t TACTL() const
+  {
+    return (static_cast<uint32_t>((reg_2890 >> 8) & 0x7) << 0);
+  }
+  void TACTL(const uint32_t v)
+  {
+    reg_2890 = (((v >> 0) & 0x7) << 8) | (reg_2890 & 0xf8ff);
+  }
+
+  uint32_t TIMA() const
+  {
+    return (static_cast<uint32_t>((reg_2890 >> 0) & 0xff) << 0);
+  }
+  void TIMA(const uint32_t v)
+  {
+    reg_2890 = (((v >> 0) & 0xff) << 0) | (reg_2890 & 0xff00);
+  }
+
+  uint32_t TBCTL() const
+  {
+    return (static_cast<uint32_t>((reg_2894 >> 8) & 0x7) << 0);
+  }
+  void TBCTL(const uint32_t v)
+  {
+    reg_2894 = (((v >> 0) & 0x7) << 8) | (reg_2894 & 0xf8ff);
+  }
+
+  uint32_t TIMB() const
+  {
+    return (static_cast<uint32_t>((reg_2894 >> 0) & 0xff) << 0);
+  }
+  void TIMB(const uint32_t v)
+  {
+    reg_2894 = (((v >> 0) & 0xff) << 0) | (reg_2894 & 0xff00);
+  }
+
+  uint32_t TCCTL() const
+  {
+    return (static_cast<uint32_t>((reg_2898 >> 8) & 0x7) << 0);
+  }
+  void TCCTL(const uint32_t v)
+  {
+    reg_2898 = (((v >> 0) & 0x7) << 8) | (reg_2898 & 0xf8ff);
+  }
+
+  uint32_t TIMC() const
+  {
+    return (static_cast<uint32_t>((reg_2898 >> 0) & 0xff) << 0);
+  }
+  void TIMC(const uint32_t v)
+  {
+    reg_2898 = (((v >> 0) & 0xff) << 0) | (reg_2898 & 0xff00);
+  }
+
+  uint32_t SCIEB() const
+  {
+    return (static_cast<uint32_t>((reg_289c >> 0) & 0x7ff) << 0);
+  }
+  void SCIEB(const uint32_t v)
+  {
+    reg_289c = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t SCIPD() const
+  {
+    return (static_cast<uint32_t>((reg_28a0 >> 0) & 0x7ff) << 0);
+  }
+  void SCIPD(const uint32_t v)
+  {
+    reg_28a0 = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t SCIRE() const
+  {
+    return (static_cast<uint32_t>((reg_28a4 >> 0) & 0x7ff) << 0);
+  }
+  void SCIRE(const uint32_t v)
+  {
+    reg_28a4 = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t SCILV0() const
+  {
+    return (static_cast<uint32_t>((reg_28a8 >> 0) & 0xff) << 0);
+  }
+  void SCILV0(const uint32_t v)
+  {
+    reg_28a8 = (((v >> 0) & 0xff) << 0);
+  }
+
+  uint32_t SCILV1() const
+  {
+    return (static_cast<uint32_t>((reg_28ac >> 0) & 0xff) << 0);
+  }
+  void SCILV1(const uint32_t v)
+  {
+    reg_28ac = (((v >> 0) & 0xff) << 0);
+  }
+
+  uint32_t SCILV2() const
+  {
+    return (static_cast<uint32_t>((reg_28b0 >> 0) & 0xff) << 0);
+  }
+  void SCILV2(const uint32_t v)
+  {
+    reg_28b0 = (((v >> 0) & 0xff) << 0);
+  }
+
+  uint32_t MCIEB() const
+  {
+    return (static_cast<uint32_t>((reg_28b4 >> 0) & 0x7ff) << 0);
+  }
+  void MCIEB(const uint32_t v)
+  {
+    reg_28b4 = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t MCIPB() const
+  {
+    return (static_cast<uint32_t>((reg_28b8 >> 0) & 0x7ff) << 0);
+  }
+  void MCIPB(const uint32_t v)
+  {
+    reg_28b8 = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t MCIRE() const
+  {
+    return (static_cast<uint32_t>((reg_28bc >> 0) & 0x7ff) << 0);
+  }
+  void MCIRE(const uint32_t v)
+  {
+    reg_28bc = (((v >> 0) & 0x7ff) << 0);
+  }
+
+  uint32_t VREG() const
+  {
+    return (static_cast<uint32_t>((reg_2c00 >> 8) & 0x3) << 0);
+  }
+  void VREG(const uint32_t v)
+  {
+    reg_2c00 = (((v >> 0) & 0x3) << 8) | (reg_2c00 & 0xfcff);
+  }
+
+  uint32_t ARMRST() const
+  {
+    return (static_cast<uint32_t>((reg_2c00 >> 0) & 0x1) << 0);
+  }
+  void ARMRST(const uint32_t v)
+  {
+    reg_2c00 = (((v >> 0) & 0x1) << 0) | (reg_2c00 & 0xfffe);
+  }
+
+  uint32_t L7() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 7) & 0x1) << 0);
+  }
+  void L7(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 7) | (reg_2d00 & 0xff7f);
+  }
+
+  uint32_t L6() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 6) & 0x1) << 0);
+  }
+  void L6(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 6) | (reg_2d00 & 0xffbf);
+  }
+
+  uint32_t L5() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 5) & 0x1) << 0);
+  }
+  void L5(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 5) | (reg_2d00 & 0xffdf);
+  }
+
+  uint32_t L4() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 4) & 0x1) << 0);
+  }
+  void L4(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 4) | (reg_2d00 & 0xffef);
+  }
+
+  uint32_t L3() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 3) & 0x1) << 0);
+  }
+  void L3(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 3) | (reg_2d00 & 0xfff7);
+  }
+
+  uint32_t L2() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 2) & 0x1) << 0);
+  }
+  void L2(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 2) | (reg_2d00 & 0xfffb);
+  }
+
+  uint32_t L1() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 1) & 0x1) << 0);
+  }
+  void L1(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 1) | (reg_2d00 & 0xfffd);
+  }
+
+  uint32_t L0() const
+  {
+    return (static_cast<uint32_t>((reg_2d00 >> 0) & 0x1) << 0);
+  }
+  void L0(const uint32_t v)
+  {
+    reg_2d00 = (((v >> 0) & 0x1) << 0) | (reg_2d00 & 0xfffe);
+  }
+
+  uint32_t RP() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 8) & 0x1) << 0);
+  }
+  void RP(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 8) | (reg_2d04 & 0xfeff);
+  }
+
+  uint32_t M7() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 7) & 0x1) << 0);
+  }
+  void M7(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 7) | (reg_2d04 & 0xff7f);
+  }
+
+  uint32_t M6() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 6) & 0x1) << 0);
+  }
+  void M6(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 6) | (reg_2d04 & 0xffbf);
+  }
+
+  uint32_t M5() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 5) & 0x1) << 0);
+  }
+  void M5(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 5) | (reg_2d04 & 0xffdf);
+  }
+
+  uint32_t M4() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 4) & 0x1) << 0);
+  }
+  void M4(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 4) | (reg_2d04 & 0xffef);
+  }
+
+  uint32_t M3() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 3) & 0x1) << 0);
+  }
+  void M3(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 3) | (reg_2d04 & 0xfff7);
+  }
+
+  uint32_t M2() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 2) & 0x1) << 0);
+  }
+  void M2(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 2) | (reg_2d04 & 0xfffb);
+  }
+
+  uint32_t M1() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 1) & 0x1) << 0);
+  }
+  void M1(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 1) | (reg_2d04 & 0xfffd);
+  }
+
+  uint32_t M0() const
+  {
+    return (static_cast<uint32_t>((reg_2d04 >> 0) & 0x1) << 0);
+  }
+  void M0(const uint32_t v)
+  {
+    reg_2d04 = (((v >> 0) & 0x1) << 0) | (reg_2d04 & 0xfffe);
+  }
+
+};
+
+static_assert((sizeof (aica_common)) == 0x2d08 - 0x2800);
+static_assert((offsetof (aica_common, reg_2800)) == 0x2800 - 0x2800);
+static_assert((offsetof (aica_common, reg_2804)) == 0x2804 - 0x2800);
+static_assert((offsetof (aica_common, reg_2808)) == 0x2808 - 0x2800);
+static_assert((offsetof (aica_common, reg_280c)) == 0x280c - 0x2800);
+static_assert((offsetof (aica_common, reg_2810)) == 0x2810 - 0x2800);
+static_assert((offsetof (aica_common, reg_2814)) == 0x2814 - 0x2800);
+static_assert((offsetof (aica_common, reg_2880)) == 0x2880 - 0x2800);
+static_assert((offsetof (aica_common, reg_2884)) == 0x2884 - 0x2800);
+static_assert((offsetof (aica_common, reg_2888)) == 0x2888 - 0x2800);
+static_assert((offsetof (aica_common, reg_288c)) == 0x288c - 0x2800);
+static_assert((offsetof (aica_common, reg_2890)) == 0x2890 - 0x2800);
+static_assert((offsetof (aica_common, reg_2894)) == 0x2894 - 0x2800);
+static_assert((offsetof (aica_common, reg_2898)) == 0x2898 - 0x2800);
+static_assert((offsetof (aica_common, reg_289c)) == 0x289c - 0x2800);
+static_assert((offsetof (aica_common, reg_28a0)) == 0x28a0 - 0x2800);
+static_assert((offsetof (aica_common, reg_28a4)) == 0x28a4 - 0x2800);
+static_assert((offsetof (aica_common, reg_28a8)) == 0x28a8 - 0x2800);
+static_assert((offsetof (aica_common, reg_28ac)) == 0x28ac - 0x2800);
+static_assert((offsetof (aica_common, reg_28b0)) == 0x28b0 - 0x2800);
+static_assert((offsetof (aica_common, reg_28b4)) == 0x28b4 - 0x2800);
+static_assert((offsetof (aica_common, reg_28b8)) == 0x28b8 - 0x2800);
+static_assert((offsetof (aica_common, reg_28bc)) == 0x28bc - 0x2800);
+static_assert((offsetof (aica_common, reg_2c00)) == 0x2c00 - 0x2800);
+static_assert((offsetof (aica_common, reg_2d00)) == 0x2d00 - 0x2800);
+static_assert((offsetof (aica_common, reg_2d04)) == 0x2d04 - 0x2800);
diff --git a/aica/aica_dsp_out.hpp b/aica/aica_dsp_out.hpp
new file mode 100644
index 0000000..77dffa6
--- /dev/null
+++ b/aica/aica_dsp_out.hpp
@@ -0,0 +1,31 @@
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+struct aica_dsp_out {
+  reg16 reg_0000;
+  const reg16 _pad0[1];
+
+  uint32_t EFDSL() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 8) & 0xf) << 0);
+  }
+  void EFDSL(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0xf) << 8) | (reg_0000 & 0xf0ff);
+  }
+
+  uint32_t EFPAN() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 0) & 0x1f) << 0);
+  }
+  void EFPAN(const uint32_t v)
+  {
+    reg_0000 = (((v >> 0) & 0x1f) << 0) | (reg_0000 & 0xffe0);
+  }
+
+};
+
+static_assert((sizeof (aica_dsp_out)) == 0x4 - 0x0);
+static_assert((offsetof (aica_dsp_out, reg_0000)) == 0x0 - 0x0);
diff --git a/aica/aica_rtc.hpp b/aica/aica_rtc.hpp
new file mode 100644
index 0000000..4c69d8b
--- /dev/null
+++ b/aica/aica_rtc.hpp
@@ -0,0 +1,38 @@
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+struct aica_rtc {
+  reg16 reg_0000;
+  const reg16 _pad0[1];
+  reg16 reg_0004;
+  const reg16 _pad1[1];
+  reg16 reg_0008;
+  const reg16 _pad2[1];
+
+  uint32_t RTC() const
+  {
+    return (static_cast<uint32_t>((reg_0000 >> 0) & 0xffff) << 16) | (static_cast<uint32_t>((reg_0004 >> 0) & 0xffff) << 0);
+  }
+  void RTC(const uint32_t v)
+  {
+    reg_0000 = (((v >> 16) & 0xffff) << 0);
+    reg_0004 = (((v >> 0) & 0xffff) << 0);
+  }
+
+  uint32_t EN() const
+  {
+    return (static_cast<uint32_t>((reg_0008 >> 0) & 0x1) << 0);
+  }
+  void EN(const uint32_t v)
+  {
+    reg_0008 = (((v >> 0) & 0x1) << 0);
+  }
+
+};
+
+static_assert((sizeof (aica_rtc)) == 0xc - 0x0);
+static_assert((offsetof (aica_rtc, reg_0000)) == 0x0 - 0x0);
+static_assert((offsetof (aica_rtc, reg_0004)) == 0x4 - 0x0);
+static_assert((offsetof (aica_rtc, reg_0008)) == 0x8 - 0x0);
diff --git a/common.mk b/common.mk
index 20f52e6..343e6c0 100644
--- a/common.mk
+++ b/common.mk
@@ -2,7 +2,7 @@ MAKEFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
 DIR := $(dir $(MAKEFILE_PATH))
 
 LIB ?= .
-OPT ?= -O2
+OPT ?= -O0
 DEBUG ?= -g -gdwarf-4
 GENERATED ?=
 
@@ -169,6 +169,18 @@ gdrom/gdrom_bits.hpp: regs/gdrom_bits.csv regs/gen/core_bits.py
 gdrom/command_packet_format.hpp: regs/gdrom_command_packet_format.csv regs/gen/gdrom_command_packet_format.py regs/gen/generic_sparse_struct.py
 	python regs/gen/gdrom_command_packet_format.py $< gdrom_command_packet_format > $@
 
+aica/aica_channel.hpp: regs/aica_channel_data.csv regs/gen/aica.py
+	python regs/gen/aica.py $< aica_channel 0x80 > $@
+
+aica/aica_common.hpp: regs/aica_common_data.csv regs/gen/aica.py
+	python regs/gen/aica.py $< aica_common > $@
+
+aica/aica_rtc.hpp: regs/aica_rtc_data.csv regs/gen/aica.py
+	python regs/gen/aica.py $< aica_rtc > $@
+
+aica/aica_dsp_out.hpp: regs/aica_dsp_out_data.csv regs/gen/aica.py
+	python regs/gen/aica.py $< aica_dsp_out > $@
+
 iso9660/%.hpp: iso9660/%.csv iso9660/byte_position.py
 	python iso9660/byte_position.py $< > $@
 
diff --git a/regs/aica_channel_data.csv b/regs/aica_channel_data.csv
new file mode 100644
index 0000000..1a0a6c1
--- /dev/null
+++ b/regs/aica_channel_data.csv
@@ -0,0 +1,42 @@
+"name","part","address","register_bits","argument_bits"
+"KYONEX",,"0x0000","15",
+"KYONB",,"0x0000","14",
+"SSCTL",,"0x0000","10",
+"LPCTL",,"0x0000","9",
+"PCMS",,"0x0000","8-7",
+"SA","0","0x0000","6-0","22-16"
+"SA","1","0x0004","15-0",
+"LSA",,"0x0008","15-0",
+"LEA",,"0x000c","15-0",
+"D2R",,"0x0010","15-11",
+"D1R",,"0x0010","10-6",
+"AR",,"0x0010","4-0",
+"LPSLNK",,"0x0014","14",
+"KRS",,"0x0014","13-10",
+"DL",,"0x0014","9-5",
+"RR",,"0x0014","4-0",
+"OCT",,"0x0018","14-11",
+"FNS",,"0x0018","9-0",
+"LFORE",,"0x001c","15",
+"LFOF",,"0x001c","14-10",
+"PLFOWS",,"0x001c","9-8",
+"PLFOS",,"0x001c","7-5",
+"ALFOWS",,"0x001c","4-3",
+"ALFOS",,"0x001c","2-0",
+"IMXL",,"0x0020","7-4",
+"ISEL",,"0x0020","3-0",
+"DISDL",,"0x0024","11-8",
+"DIPAN",,"0x0024","4-0",
+"TL",,"0x0028","15-8",
+"VOFF",,"0x0028","6",
+"LPOFF",,"0x0028","5",
+"Q",,"0x0028","4-0",
+"FLV0",,"0x002c","12-0",
+"FLV1",,"0x0030","12-0",
+"FLV2",,"0x0034","12-0",
+"FLV3",,"0x0038","12-0",
+"FLV4",,"0x003c","12-0",
+"FAR",,"0x0040","12-8",
+"FD1R",,"0x0040","4-0",
+"FD2R",,"0x0044","12-8",
+"FRR",,"0x0044","4-0",
diff --git a/regs/aica_channel_data.ods b/regs/aica_channel_data.ods
index 62e5ea4..7add0c2 100644
Binary files a/regs/aica_channel_data.ods and b/regs/aica_channel_data.ods differ
diff --git a/regs/aica_common_data.csv b/regs/aica_common_data.csv
new file mode 100644
index 0000000..f9b3969
--- /dev/null
+++ b/regs/aica_common_data.csv
@@ -0,0 +1,66 @@
+"name","part","address","register_bits","argument_bits"
+"MONO",,"0x2800","15",
+"MEM8MB",,"0x2800","9",
+"DAC18B",,"0x2800","8",
+"VER",,"0x2800","7-4",
+"MVOL",,"0x2800","3-0",
+"TESTB0",,"0x2804","15",
+"RBL",,"0x2804","14-13",
+"RBP",,"0x2804","11-0","22-11"
+"MOFUL",,"0x2808","12",
+"MOEMP",,"0x2808","11",
+"MIOVF",,"0x2808","10",
+"MIFUL",,"0x2808","9",
+"MIEMP",,"0x2808","8",
+"MIBUF",,"0x2808","7-0",
+"AFSET",,"0x280c","14",
+"MSLC",,"0x280c","13-8",
+"MOBUF",,"0x280c","7-0",
+"LP",,"0x2810","15",
+"SGC",,"0x2810","14",
+"EG",,"0x2810","12-0",
+"CA",,"0x2814","15-0",
+"DMEA","0","0x2880","15-9","22-16"
+"TSCD",,"0x2880","7-5",
+"T",,"0x2880","4",
+"MRWINH",,"0x2880","3-0",
+"DMEA","1","0x2884","15-2","15-2"
+"DGATE",,"0x2888","15",
+"DRGA",,"0x2888","14-2","14-2"
+"DDIR",,"0x288c","15",
+"DLG",,"0x288c","14-2","14-2"
+"DEXE",,"0x288c","0",
+"TACTL",,"0x2890","10-8",
+"TIMA",,"0x2890","7-0",
+"TBCTL",,"0x2894","10-8",
+"TIMB",,"0x2894","7-0",
+"TCCTL",,"0x2898","10-8",
+"TIMC",,"0x2898","7-0",
+"SCIEB",,"0x289c","10-0",
+"SCIPD",,"0x28a0","10-0",
+"SCIRE",,"0x28a4","10-0",
+"SCILV0",,"0x28a8","7-0",
+"SCILV1",,"0x28ac","7-0",
+"SCILV2",,"0x28b0","7-0",
+"MCIEB",,"0x28b4","10-0",
+"MCIPB",,"0x28b8","10-0",
+"MCIRE",,"0x28bc","10-0",
+"VREG",,"0x2c00","9-8",
+"ARMRST",,"0x2c00","0",
+"L7",,"0x2d00","7",
+"L6",,"0x2d00","6",
+"L5",,"0x2d00","5",
+"L4",,"0x2d00","4",
+"L3",,"0x2d00","3",
+"L2",,"0x2d00","2",
+"L1",,"0x2d00","1",
+"L0",,"0x2d00","0",
+"RP",,"0x2d04","8",
+"M7",,"0x2d04","7",
+"M6",,"0x2d04","6",
+"M5",,"0x2d04","5",
+"M4",,"0x2d04","4",
+"M3",,"0x2d04","3",
+"M2",,"0x2d04","2",
+"M1",,"0x2d04","1",
+"M0",,"0x2d04","0",
diff --git a/regs/aica_common_data.ods b/regs/aica_common_data.ods
index 5c51f67..8cb9e2d 100644
Binary files a/regs/aica_common_data.ods and b/regs/aica_common_data.ods differ
diff --git a/regs/aica_dsp_out_data.csv b/regs/aica_dsp_out_data.csv
new file mode 100644
index 0000000..aabf8fd
--- /dev/null
+++ b/regs/aica_dsp_out_data.csv
@@ -0,0 +1,3 @@
+"name","part","address","register_bits","argument_bits"
+"EFDSL",,"0x0000","11-8",
+"EFPAN",,"0x0000","4-0",
diff --git a/regs/aica_dsp_out_data.ods b/regs/aica_dsp_out_data.ods
new file mode 100644
index 0000000..00e54cc
Binary files /dev/null and b/regs/aica_dsp_out_data.ods differ
diff --git a/regs/aica_rtc_data.csv b/regs/aica_rtc_data.csv
new file mode 100644
index 0000000..92e55b6
--- /dev/null
+++ b/regs/aica_rtc_data.csv
@@ -0,0 +1,4 @@
+"name","part","address","register_bits","argument_bits"
+"RTC","0","0x0000","15-0","31-16"
+"RTC","1","0x0004","15-0","15-0"
+"EN",,"0x0008","0",
diff --git a/regs/aica_rtc_data.ods b/regs/aica_rtc_data.ods
index 8a02ab6..05827ab 100644
Binary files a/regs/aica_rtc_data.ods and b/regs/aica_rtc_data.ods differ
diff --git a/regs/gen/aica.py b/regs/gen/aica.py
new file mode 100644
index 0000000..7c8e1b8
--- /dev/null
+++ b/regs/gen/aica.py
@@ -0,0 +1,200 @@
+import sys
+from dataclasses import dataclass
+from collections import defaultdict
+
+from generate import renderer
+from csv_input import read_input
+
+@dataclass
+class Part:
+    index: int
+    address: int
+    register_bits: tuple[int, int]
+    argument_bits: tuple[int, int]
+
+@dataclass
+class Register:
+    name: str
+    parts: list[Part]
+
+def parse_slice(s):
+    if '-' in s:
+        start0, end0 = s.split('-')
+        start, end = int(start0, 10), int(end0, 10)
+        assert start > end, s
+        return start, end
+    else:
+        start = int(s, 10)
+        return start, start
+
+def slice_bits(s):
+    start, end = s
+    return set(range(start, end+1))
+
+def parse_row(row):
+    address = int(row["address"], 16)
+    name = row["name"]
+    part_index0 = row["part"].strip()
+    part_index = int(part_index0, 10) if part_index0 else 0
+
+    register_bits = parse_slice(row["register_bits"])
+    if row["argument_bits"].strip():
+        argument_bits = parse_slice(row["argument_bits"])
+        assert len(slice_bits(argument_bits)) == len(slice_bits(register_bits)), row
+    else:
+        start, end = register_bits
+        argument_bits = (start - end, 0)
+
+    part = Part(
+        part_index,
+        address,
+        register_bits,
+        argument_bits,
+    )
+    return name, part
+
+def group_parts(rows, address_increment):
+    by_name: dict[str, Register] = {}
+    register_bit_alloc: dict[int, set[int]] = defaultdict(set)
+    argument_bit_alloc: dict[str, set[int]] = defaultdict(set)
+    register_order = []
+    addresses = []
+    last_address = 0
+
+    for row in rows:
+        name, part = parse_row(row)
+        assert part.address >= last_address, row
+        assert part.address % address_increment == 0, row
+        last_address = part.address
+        if part.address not in set(a[0] for a in addresses):
+            addresses.append((part.address, [name]))
+        else:
+            assert addresses[-1][0] == part.address
+            addresses[-1][1].append(name)
+
+        bits = slice_bits(part.register_bits)
+        assert bits.intersection(register_bit_alloc[part.address]) == set(), row
+        register_bit_alloc[part.address] |= bits
+
+        bits = slice_bits(part.argument_bits)
+        assert bits.intersection(argument_bit_alloc[name]) == set(), row
+        argument_bit_alloc[part.address] |= bits
+
+        if name not in by_name:
+            assert part.index == 0, row
+            register = Register(name, [part])
+            by_name[name] = register
+            register_order.append(register)
+        else:
+            assert len(by_name[name].parts) == part.index
+            by_name[name].parts.append(part)
+
+    return addresses, register_order
+
+def format_reg(address):
+    return f"reg_{address:04x}"
+
+def render_struct_fields(struct_size, addresses, address_increment, c_type, c_type_size):
+    assert address_increment >= c_type_size
+    assert address_increment % c_type_size == 0
+    next_address = None
+    pad_index = 0
+    for address, _ in addresses:
+        if next_address is None:
+            next_address = address
+        if address != next_address:
+            assert address > next_address, (address, next_address)
+            padding = (address - next_address) // c_type_size
+            yield f"const {c_type} _pad{pad_index}[{padding}];"
+            pad_index += 1
+
+        yield f"{c_type} {format_reg(address)};"
+        if c_type_size < address_increment:
+            padding = (address_increment - c_type_size) // c_type_size
+            yield f"const {c_type} _pad{pad_index}[{padding}];"
+            pad_index += 1
+        next_address = address + address_increment
+
+    if struct_size is not None:
+        assert struct_size % address_increment == 0
+        assert struct_size >= next_address
+        if struct_size > next_address:
+            padding = (struct_size - next_address) // c_type_size
+            yield f"const {c_type} _pad{pad_index}[{padding}];"
+
+def render_struct_static_assertions(struct_name, struct_size, addresses, address_increment):
+    first_address = addresses[0][0]
+    last_address = addresses[-1][0]
+    if struct_size is None:
+        struct_size = last_address + address_increment
+    yield f"static_assert((sizeof ({struct_name})) == {hex(struct_size)} - {hex(first_address)});"
+    for address, _ in addresses:
+        yield f"static_assert((offsetof ({struct_name}, {format_reg(address)})) == {hex(address)} - {hex(first_address)});"
+
+def mask_from_bits(bit_slice):
+    h, l = bit_slice
+    mask = 2 ** ((h - l) + 1) - 1
+    return mask
+
+def part_get_expression(part):
+    _, reg_end = part.register_bits
+    _, arg_end = part.argument_bits
+    arg_mask = mask_from_bits(part.argument_bits)
+    return f"(static_cast<uint32_t>(({format_reg(part.address)} >> {reg_end}) & {hex(arg_mask)}) << {arg_end})"
+
+def part_set_statement(addresses_dict, c_type_size, part):
+    _, reg_end = part.register_bits
+    _, arg_end = part.argument_bits
+    arg_mask = mask_from_bits(part.argument_bits)
+    assignment = f"{format_reg(part.address)} = (((v >> {arg_end}) & {hex(arg_mask)}) << {reg_end})"
+    if len(addresses_dict[part.address]) > 1:
+        reg_mask = mask_from_bits(part.register_bits) << reg_end
+        inverse_mask = (~reg_mask) & ((2 ** (c_type_size * 8)) - 1)
+        assignment += f" | ({format_reg(part.address)} & {hex(inverse_mask)});"
+    else:
+        assignment += ";"
+    return assignment
+
+def render_struct_accessors(addresses_dict, c_type, c_type_size, registers):
+    for register in registers:
+        yield f"uint32_t {register.name}() const"
+        yield "{"
+        get_expression = " | ".join(map(part_get_expression, register.parts))
+        yield f"return {get_expression};"
+        yield "}"
+        yield f"void {register.name}(const uint32_t v)"
+        yield "{"
+        for part in register.parts:
+            yield part_set_statement(addresses_dict, c_type_size, part)
+        yield "}"
+        yield ""
+
+def render_struct(struct_name, struct_size, addresses, address_increment, c_type, c_type_size, registers):
+    yield f"struct {struct_name} {{"
+    yield from render_struct_fields(struct_size, addresses, address_increment, c_type, c_type_size)
+    yield ""
+    addresses_dict = dict(addresses)
+    yield from render_struct_accessors(addresses_dict, c_type, c_type_size, registers)
+    yield "};"
+    yield from render_struct_static_assertions(struct_name, struct_size, addresses, address_increment)
+
+def header():
+    yield "#include <cstdint>"
+    yield "#include <cstddef>"
+    yield ""
+    yield '#include "type.hpp"'
+    yield ""
+
+if __name__ == "__main__":
+    input_file = sys.argv[1]
+    struct_name = sys.argv[2]
+    struct_size = int(sys.argv[3], 16) if len(sys.argv) > 3 else None
+    rows = read_input(input_file)
+    address_increment = 4
+    c_type = "reg16"
+    c_type_size = 2
+    addresses, registers = group_parts(rows, address_increment)
+    render, out = renderer()
+    render(header())
+    render(render_struct(struct_name, struct_size, addresses, address_increment, c_type, c_type_size, registers))
+    sys.stdout.write(out.getvalue())
diff --git a/regs/gen/sh7091.py b/regs/gen/sh7091.py
index 1374d7f..ec64379 100644
--- a/regs/gen/sh7091.py
+++ b/regs/gen/sh7091.py
@@ -1,26 +1,7 @@
-import csv
 import sys
-from functools import partial
-from pprint import pprint
 
 from generate import renderer
-
-def as_dict(header, row0):
-    row = [s.strip() for s in row0]
-    return dict(zip(header, row))
-
-def read_input(filename):
-    with open(filename) as f:
-        reader = csv.reader(f, delimiter=",", quotechar='"')
-        header, *rows = reader
-
-    rows = [
-        as_dict(header, row)
-        for row in rows
-        if "".join(map(str, row)).strip()
-    ]
-
-    return rows
+from csv_input import read_input
 
 def size_p(size):
     return size in {1, 2, 4}
diff --git a/vga.cpp b/vga.cpp
index a5af9ad..aab1450 100644
--- a/vga.cpp
+++ b/vga.cpp
@@ -4,7 +4,7 @@
 #include "sh7091/sh7091_bits.hpp"
 #include "holly/holly.hpp"
 #include "holly/core_bits.hpp"
-#include "aica.hpp"
+#include "aica/aica.hpp"
 #include "memorymap.hpp"
 
 #include "vga.hpp"
@@ -90,10 +90,8 @@ void vga2()
                   | fb_r_ctrl::fb_depth::_0565_rgb_16bit
                   | fb_r_ctrl::fb_enable;
 
-#define DVE_OUTPUT_MODE (&aica[0x2c00])
 #define DVE_OUTPUT_MODE__VGA (0b00 << 0)
-  *DVE_OUTPUT_MODE = DVE_OUTPUT_MODE__VGA;
-#undef DVE_OUTPUT_MODE
+  aica.common.VREG(DVE_OUTPUT_MODE__VGA);
 #undef DVE_OUTPUT_MODE__VGA
 }