gdrom: add gdrom_bits

common.mk

@@ -131,7 +131,7 @@ audio.pcm:
 	$(BUILD_BINARY_O)
 
 %.csv: %.ods
-	libreoffice --headless -convert-to csv:"Text - txt - csv (StarCalc)":44,34,76,,,,true --outdir $(dir $@) $<
+	libreoffice --headless --convert-to csv:"Text - txt - csv (StarCalc)":44,34,76,,,,true --outdir $(dir $@) $<
 
 maple/maple_bus_commands.hpp: regs/maple_bus_commands.csv regs/gen/maple_bus_commands.py
 	python regs/gen/maple_bus_commands.py $< > $@
@@ -160,6 +160,9 @@ sh7091/sh7091.hpp: regs/sh7091.csv regs/gen/sh7091.py
 sh7091/sh7091_bits.hpp: regs/sh7091_bits.csv regs/gen/core_bits.py
 	python regs/gen/core_bits.py $< > $@
 
+gdrom/gdrom_bits.hpp: regs/gdrom_bits.csv regs/gen/core_bits.py
+	python regs/gen/core_bits.py $< gdrom > $@
+
 gdrom/command_packet_format.hpp: regs/gdrom_command_packet_format.csv regs/gen/gdrom_command_packet_format.py regs/gen/generic_sparse_struct.py
 	python regs/gen/gdrom_command_packet_format.py $< gdrom_command_packet_format > $@
 

example/gdrom_test.cpp

@@ -11,29 +11,28 @@ union data {
 };
 static_assert((sizeof (data)) == 2);
 
-
 void test_unit()
 {
   serial::string("test_unit\n");
   // wait for BSY == 0 && DRQ == 0
-  while ((gdrom_if.status & (gdrom::status::bsy | gdrom::status::drq)) != 0) {
+  while ((gdrom::status::bsy(gdrom_if.status) | gdrom::status::drq(gdrom_if.status)) != 0) {
     serial::integer<uint8_t>(gdrom_if.status);
     for (int i = 0; i < 1000000; i++) { asm volatile ("nop;"); }
   };
   serial::string("bsy | drq == 0\n");
 
   gdrom_if.command = 0xa0; // packet command
-  while ((gdrom_if.status & gdrom::status::drq) == 0);
+  while ((gdrom::status::drq(gdrom_if.status)) == 0);
   serial::string("drq != 0; CoD: ");
   serial::integer<uint8_t>(gdrom_if.interrupt_reason & 1);
 
   serial::string("bsy1: ");
-  serial::integer<uint8_t>(gdrom_if.status & gdrom::status::bsy);
+  serial::integer<uint8_t>(gdrom::status::bsy(gdrom_if.status));
   for (int i = 0; i < 6; i++)
     gdrom_if.data = 0;
-  serial::integer<uint8_t>(gdrom_if.status & gdrom::status::bsy);
+  serial::integer<uint8_t>(gdrom::status::bsy(gdrom_if.status));
 
-  while ((gdrom_if.status & (gdrom::status::bsy | gdrom::status::drq)) != 0);
+  while ((gdrom::status::bsy(gdrom_if.status) | gdrom::status::drq(gdrom_if.status)) != 0);
   serial::string("bsy2: ");
   serial::integer<uint8_t>(gdrom_if.status);
   serial::string("\n");
@@ -41,7 +40,7 @@ void test_unit()
 
 void pio_data(const uint8_t * data)
 {
-  while ((gdrom_if.status & (gdrom::status::bsy | gdrom::status::drq)) != 0);
+  while ((gdrom::status::bsy(gdrom_if.status) | gdrom::status::drq(gdrom_if.status)) != 0);
   serial::string("bsy | drq == 0\n");
 
   gdrom_if.features = 0; // not DMA
@@ -49,10 +48,7 @@ void pio_data(const uint8_t * data)
 
   gdrom_if.command = 0xa0; // packet command
   // CoD
-  //serial::string("wait CoD\n");
+  while (gdrom::status::drq(gdrom_if.status) == 0);
-  while ((gdrom_if.interrupt_reason & 0b11) != gdrom::interrupt_reason::cod);
-  //serial::string("done CoD\n");
-  while ((gdrom_if.status & gdrom::status::drq) == 0);
   serial::string("drq == 1\n");
 
   const uint16_t * buf = reinterpret_cast<const uint16_t *>(&data[0]);
@@ -62,7 +58,7 @@ void pio_data(const uint8_t * data)
 
   serial::string("status1: ");
   serial::integer<uint8_t>(gdrom_if.status);
-  while ((gdrom_if.status & gdrom::status::bsy) != 0) {
+  while (gdrom::status::bsy(gdrom_if.status) != 0) {
     serial::integer<uint8_t>(gdrom_if.status);
     for (int i = 0; i < 10000000; i++) { asm volatile ("nop;"); }
   };

gdrom/gdrom_bits.hpp

@@ -1,43 +1,121 @@
+#pragma once
+
 #include <cstdint>
 
+#include "../float_uint32.hpp"
+
 namespace gdrom {
+  namespace status {
+    constexpr uint32_t bsy(uint32_t reg) { return (reg >> 7) & 0x1; }
+    constexpr uint32_t drdy(uint32_t reg) { return (reg >> 6) & 0x1; }
+    constexpr uint32_t df(uint32_t reg) { return (reg >> 5) & 0x1; }
+    constexpr uint32_t dsc(uint32_t reg) { return (reg >> 4) & 0x1; }
+    constexpr uint32_t drq(uint32_t reg) { return (reg >> 3) & 0x1; }
+    constexpr uint32_t corr(uint32_t reg) { return (reg >> 2) & 0x1; }
+    constexpr uint32_t check(uint32_t reg) { return (reg >> 0) & 0x1; }
+  }
 
-namespace status {
+  namespace alternate_status {
+    constexpr uint32_t bsy(uint32_t reg) { return (reg >> 7) & 0x1; }
+    constexpr uint32_t drdy(uint32_t reg) { return (reg >> 6) & 0x1; }
+    constexpr uint32_t df(uint32_t reg) { return (reg >> 5) & 0x1; }
+    constexpr uint32_t dsc(uint32_t reg) { return (reg >> 4) & 0x1; }
+    constexpr uint32_t drq(uint32_t reg) { return (reg >> 3) & 0x1; }
+    constexpr uint32_t corr(uint32_t reg) { return (reg >> 2) & 0x1; }
+    constexpr uint32_t check(uint32_t reg) { return (reg >> 0) & 0x1; }
+  }
 
-constexpr uint8_t bsy = (1 << 7);
+  namespace command {
-constexpr uint8_t drdy = (1 << 6);
+    namespace code {
-constexpr uint8_t df = (1 << 5);
+      constexpr uint32_t soft_reset = 0x08 << 0;
-constexpr uint8_t dsc = (1 << 4);
+      constexpr uint32_t execute_device_diagnostic = 0x90 << 0;
-constexpr uint8_t drq = (1 << 3);
+      constexpr uint32_t nop = 0x00 << 0;
-constexpr uint8_t corr = (1 << 2);
+      constexpr uint32_t packet_command = 0xa0 << 0;
-constexpr uint8_t check = (1 << 0);
+      constexpr uint32_t identify_device = 0xa1 << 0;
-
+      constexpr uint32_t set_features = 0xef << 0;
-}
+
-
+      constexpr uint32_t bit_mask = 0xff << 0;
-namespace interrupt_reason {
+    }
-
+  }
-constexpr uint8_t io = (1 << 1);
+
-constexpr uint8_t cod = (1 << 0);
+  namespace device_control {
-
+    constexpr uint32_t device_control = 0b1000 << 0;
-}
+    constexpr uint32_t srst = 1 << 2;
-
+    constexpr uint32_t nien = 1 << 1;
-namespace command {
+  }
-
+
-constexpr uint8_t test_unit = 0x00;
+  namespace drive_select {
-constexpr uint8_t req_stat = 0x10;
+    constexpr uint32_t drive_select = 0b1010 << 4;
-constexpr uint8_t req_mode = 0x11;
+    constexpr uint32_t lun(uint32_t num) { return (num & 0xf) << 0; }
-constexpr uint8_t set_mode = 0x12;
+  }
-constexpr uint8_t req_error = 0x13;
+
-constexpr uint8_t get_toc = 0x14;
+  namespace error {
-constexpr uint8_t req_ses = 0x15;
+    constexpr uint32_t sense_key(uint32_t reg) { return (reg >> 4) & 0xf; }
-constexpr uint8_t cd_open = 0x16;
+    constexpr uint32_t mcr(uint32_t reg) { return (reg >> 3) & 0x1; }
-constexpr uint8_t cd_play = 0x20;
+    constexpr uint32_t abrt(uint32_t reg) { return (reg >> 2) & 0x1; }
-constexpr uint8_t cd_seek = 0x21;
+    constexpr uint32_t eomf(uint32_t reg) { return (reg >> 1) & 0x1; }
-constexpr uint8_t cd_scan = 0x22;
+    constexpr uint32_t ili(uint32_t reg) { return (reg >> 0) & 0x1; }
-constexpr uint8_t cd_read = 0x30;
+  }
-constexpr uint8_t cd_read2 = 0x31;
+
-constexpr uint8_t get_scd = 0x40;
+  namespace features {
-
+    namespace dma {
-}
+      constexpr uint32_t disable = 0 << 0;
+      constexpr uint32_t enable = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace features_ata {
+    namespace set_clear {
+      constexpr uint32_t clear = 0 << 7;
+      constexpr uint32_t set = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace command {
+      constexpr uint32_t set_transfer_mode = 3 << 0;
+
+      constexpr uint32_t bit_mask = 0x7f << 0;
+    }
+  }
+
+  namespace interrupt_reason {
+    constexpr uint32_t io(uint32_t reg) { return (reg >> 1) & 0x1; }
+    constexpr uint32_t cod(uint32_t reg) { return (reg >> 0) & 0x1; }
+  }
+
+  namespace sector_count {
+    namespace transfer_mode {
+      constexpr uint32_t pio_default_transfer_mode = 0b00000000 << 0;
+      constexpr uint32_t pio_flow_control_transfer_mode = 0b00001000 << 0;
+      constexpr uint32_t single_word_dma_mode = 0b00010000 << 0;
+      constexpr uint32_t multi_word_dma_mode = 0b00100000 << 0;
+
+      constexpr uint32_t bit_mask = 0xff << 0;
+    }
+  }
+
+  namespace sector_number {
+    constexpr uint32_t disc_format(uint32_t reg) { return (reg >> 4) & 0xf; }
+    constexpr uint32_t status(uint32_t reg) { return (reg >> 0) & 0xf; }
+  }
+
+  namespace error_ata {
+    namespace sense_key {
+      constexpr uint32_t no_sense = 0x0 << 0;
+      constexpr uint32_t recovered_error = 0x1 << 0;
+      constexpr uint32_t not_ready = 0x2 << 0;
+      constexpr uint32_t medium_error = 0x3 << 0;
+      constexpr uint32_t hardware_error = 0x4 << 0;
+      constexpr uint32_t illegal_request = 0x5 << 0;
+      constexpr uint32_t unit_attention = 0x6 << 0;
+      constexpr uint32_t data_protect = 0x7 << 0;
+      constexpr uint32_t aborted_command = 0xb << 0;
+
+      constexpr uint32_t bit_mask = 0xf << 0;
+    }
+  }
 
 }

regs/gdrom_bits.csv

@@ -0,0 +1,64 @@
+"register_name","enum_name","bits","bit_name","value","mask","description"
+"status",,"7","bsy",,,
+"status",,"6","drdy",,,
+"status",,"5","df",,,
+"status",,"4","dsc",,,
+"status",,"3","drq",,,
+"status",,"2","corr",,,
+"status",,"0","check",,,
+,,,,,,
+"alternate_status",,"7","bsy",,,
+"alternate_status",,"6","drdy",,,
+"alternate_status",,"5","df",,,
+"alternate_status",,"4","dsc",,,
+"alternate_status",,"3","drq",,,
+"alternate_status",,"2","corr",,,
+"alternate_status",,"0","check",,,
+,,,,,,
+"command","code","7-0","soft_reset","0x08",,
+"command","code","7-0","execute_device_diagnostic","0x90",,
+"command","code","7-0","nop","0x00",,
+"command","code","7-0","packet_command","0xa0",,
+"command","code","7-0","identify_device","0xa1",,
+"command","code","7-0","set_features","0xef",,
+,,,,,,
+"device_control",,"3,0","device_control","0b1000",,
+"device_control",,"2","srst","1",,
+"device_control",,"1","nien","1",,
+,,,,,,
+"drive_select",,"7-4","drive_select","0b1010",,
+"drive_select",,"3-0","lun",,"0xf",
+,,,,,,
+"error",,"7-4","sense_key",,,
+"error",,"3","mcr",,,
+"error",,"2","abrt",,,
+"error",,"1","eomf",,,
+"error",,"0","ili",,,
+,,,,,,
+"features","dma","0","disable","0",,
+"features","dma","0","enable","1",,
+,,,,,,
+"features_ata","set_clear","7","clear","0",,
+"features_ata","set_clear","7","set","1",,
+"features_ata","command","6-0","set_transfer_mode","3",,
+,,,,,,
+"interrupt_reason",,"1","io",,,
+"interrupt_reason",,"0","cod",,,
+,,,,,,
+"sector_count","transfer_mode","7-0","pio_default_transfer_mode","0b00000000",,
+"sector_count","transfer_mode","7-0","pio_flow_control_transfer_mode","0b00001000",,
+"sector_count","transfer_mode","7-0","single_word_dma_mode","0b00010000",,
+"sector_count","transfer_mode","7-0","multi_word_dma_mode","0b00100000",,
+,,,,,,
+"sector_number",,"7-4","disc_format",,,
+"sector_number",,"3-0","status",,,
+,,,,,,
+"error_ata","sense_key","3-0","no_sense","0x0",,
+"error_ata","sense_key","3-0","recovered_error","0x1",,
+"error_ata","sense_key","3-0","not_ready","0x2",,
+"error_ata","sense_key","3-0","medium_error","0x3",,
+"error_ata","sense_key","3-0","hardware_error","0x4",,
+"error_ata","sense_key","3-0","illegal_request","0x5",,
+"error_ata","sense_key","3-0","unit_attention","0x6",,
+"error_ata","sense_key","3-0","data_protect","0x7",,
+"error_ata","sense_key","3-0","aborted_command","0xb",,

regs/gen/core_bits.py

@@ -41,9 +41,9 @@ def aggregate_enums(aggregated_rows):
     all_bits = set()
     enum_bits = dict()
 
-    def assert_unique_ordered(bits):
+    def assert_unique_ordered(bits, row):
         nonlocal all_bits
-        assert all(bit not in all_bits for bit in bits), bits
+        assert all(bit not in all_bits for bit in bits), (bits, row)
         assert max(all_bits, default=32) > max(bits), (all_bits, bits)
         all_bits |= bits
 
@@ -51,11 +51,11 @@ def aggregate_enums(aggregated_rows):
         bits = parse_bit_range(row["bits"])
         assert row["bit_name"] != "", row
         if row["enum_name"] == "":
-            assert_unique_ordered(bits)
+            assert_unique_ordered(bits, row)
             non_enum.append(row)
         else:
             if row["enum_name"] not in enum_bits:
-                assert_unique_ordered(bits)
+                assert_unique_ordered(bits, row)
                 non_enum.append(row["enum_name"])
             else:
                 assert enum_bits[row["enum_name"]] == bits, row