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cache: clear all instruction/operand caches

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This commit is contained in:
Zack Buhman 2023-10-12 09:43:54 -07:00
parent a4ac9fa4c8
commit 2bcf1aedef
9 changed files with 319 additions and 227 deletions
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25
cache.c Normal file
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@ -0,0 +1,25 @@
#include "type.h"
#include "sh7091.h"
#include "sh7091_bits.h"
#include "cache.h"
extern volatile reg32 SH7091_IC_A[256][(1 << 5) / 4] __asm("SH7091_IC_A");
extern volatile reg32 SH7091_OC_A[512][(1 << 5) / 4] __asm("SH7091_OC_A");
void cache_init()
{
for (int i = 0; i < 256; i++) {
SH7091_IC_A[i][0] = 0;
}
for (int i = 0; i < 512; i++) {
SH7091_OC_A[i][0] = 0;
}
SH7091.CCN.CCR = CCR__ICI | CCR__ICE | CCR__OCI | CCR__OCE;
SH7091.CCN.MMUCR = 0;
asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;");
}

3
cache.h Normal file
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@ -0,0 +1,3 @@
#pragma once
void cache_init() __attribute__ ((section (".p2ram.cache_init")));

10
common.mk
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@ -1,5 +1,5 @@
LIB ?= . LIB ?= .
OPT ?= -Og OPT ?= -Os
DEBUG ?= -g -gdwarf-4 DEBUG ?= -g -gdwarf-4
GENERATED ?= GENERATED ?=
@ -53,7 +53,13 @@ all: main.elf
%.o: %.c %.c.d %.o: %.c %.c.d
$(CC) $(CARCH) $(CFLAGS) $(OPT) $(DEBUG) -c $< -o $@ $(CC) $(CARCH) $(CFLAGS) $(OPT) $(DEBUG) -c $< -o $@
main.elf: main.o %.cpp.d: | $(GENERATED)
$(CXX) $(CARCH) $(CFLAGS) $(CXXFLAGS) $(OPT) $(DEBUG) $(DEPFLAGS) -c $(basename $@) -MF $@ -o /dev/null
%.o: %.cpp %.cpp.d
$(CXX) $(CARCH) $(CFLAGS) $(CXXFLAGS) $(OPT) $(DEBUG) -c $< -o $@
main.elf: start.o main.o cache.o
$(LD) $(LDFLAGS) -T $(LIB)/main.lds $^ -o $@ $(LD) $(LDFLAGS) -T $(LIB)/main.lds $^ -o $@
%.bin: %.elf %.bin: %.elf

26
main.c
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@ -1,26 +1,25 @@
#include <stdint.h> #include <stdint.h>
volatile uint8_t * SCFTDR2 = (volatile uint8_t *)0xFFE8000C; #include "cache.h"
volatile uint32_t * SOFT_RESET = (volatile uint32_t *)0xa05f8008; #include "sh7091.h"
volatile uint32_t * STARTRENDER = (volatile uint32_t *)0xa05f8014;
volatile uint32_t * VO_CONTROL = (volatile uint32_t *)0xa05f80e8;
volatile uint32_t * VO_BORDER_COL = (volatile uint32_t *)0xa05f8040;
volatile uint32_t * FB_R_SOF1 = (volatile uint32_t *)0xa05f8050;
volatile uint32_t * RAM = (volatile uint32_t *)0xa5000000; volatile uint32_t * RAM = (volatile uint32_t *)0xa5000000;
volatile uint32_t * SPG_STATUS = (volatile uint32_t *)0xa05f810; volatile uint32_t * SPG_STATUS = (volatile uint32_t *)0xa05f810;
void start() void main()
{ {
*SCFTDR2 = 'H'; cache_init();
*SCFTDR2 = 'e';
*SCFTDR2 = 'l';
*SCFTDR2 = 'l';
*SCFTDR2 = '3';
// clear BSS
SH7091.SCIF.SCFTDR2 = 'H';
SH7091.SCIF.SCFTDR2 = 'e';
SH7091.SCIF.SCFTDR2 = 'l';
SH7091.SCIF.SCFTDR2 = 'o';
/*
*SOFT_RESET = 0b111; *SOFT_RESET = 0b111;
*SOFT_RESET = 0b000; *SOFT_RESET = 0b000;
@ -30,6 +29,7 @@ void start()
for (int i = 0; i < (2*1024*1024 + 1024 * 2 + 512 + 4) / 4; i++) { for (int i = 0; i < (2*1024*1024 + 1024 * 2 + 512 + 4) / 4; i++) {
RAM[i] = 0x1; RAM[i] = 0x1;
} }
*/
while (1) { while (1) {
} }

35
main.lds
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@ -1,7 +1,8 @@
OUTPUT_FORMAT("elf32-shl", "elf32-shl", "elf32-shl") OUTPUT_FORMAT("elf32-shl", "elf32-shl", "elf32-shl")
MEMORY MEMORY
{ {
ram : ORIGIN = 0x8c010000, LENGTH = 1M p1ram : ORIGIN = 0x8c010000, LENGTH = 16M
p2ram : ORIGIN = 0xac010000, LENGTH = 16M
} }
SECTIONS SECTIONS
{ {
@ -10,33 +11,44 @@ SECTIONS
.text ALIGN(4) : SUBALIGN(4) .text ALIGN(4) : SUBALIGN(4)
{ {
KEEP(*(.text.start)) KEEP(*(.text.start))
*(.text) *(.text.startup.*)
*(.text.*) *(.text.*)
} > ram *(.text)
} > p1ram
.data ALIGN(4) : SUBALIGN(4) .data ALIGN(4) : SUBALIGN(4)
{ {
*(.data) *(.data)
*(.data.*) *(.data.*)
} > ram } > p1ram
.rodata ALIGN(4) : SUBALIGN(4) .rodata ALIGN(4) : SUBALIGN(4)
{ {
*(.rodata) *(.rodata)
*(.rodata.*) *(.rodata.*)
} > ram } > p1ram
.ctors ALIGN(4) : SUBALIGN(4) .ctors ALIGN(4) : SUBALIGN(4)
{ {
KEEP(*(.ctors)) KEEP(*(.ctors))
KEEP(*(.ctors.*)) KEEP(*(.ctors.*))
} > ram } > p1ram
.bss ALIGN(4) (NOLOAD) : SUBALIGN(4) .bss ALIGN(4) (NOLOAD) : SUBALIGN(4)
{ {
*(.bss) *(.bss)
*(.bss.*) *(.bss.*)
} > ram } > p1ram
__p1ram_end = .;
. = 0xac010000 + __p1ram_end - __p1ram_start;
.text.p2ram ALIGN(4) : SUBALIGN(4)
{
*(.p2ram)
*(.p2ram.*)
} > p2ram AT>p1ram
/DISCARD/ : /DISCARD/ :
{ {
@ -51,3 +63,12 @@ SECTIONS
__ctors_link_start = ADDR(.ctors); __ctors_link_start = ADDR(.ctors);
__ctors_link_end = ADDR(.ctors) + SIZEOF(.ctors); __ctors_link_end = ADDR(.ctors) + SIZEOF(.ctors);
} }
SH7091_IC_A = 0xf0000000;
SH7091_IC_D = 0xf1000000;
SH7091_OC_A = 0xf4000000;
SH7091_OC_D = 0xf5000000;
SH7091 = 0xff000000;
HOLLY = 0xa05f8000;
__p1ram_start = ORIGIN(p1ram);
__p1ram_end = ORIGIN(p1ram) + LENGTH(p1ram);

12
regs/gen/sh7091.py
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@ -26,11 +26,11 @@ def size_p(size):
def size_to_type(size): def size_to_type(size):
if size == 1: if size == 1:
return "uint8_t " return "reg8 "
elif size == 2: elif size == 2:
return "uint16_t" return "reg16"
elif size == 4: elif size == 4:
return "uint32_t" return "reg32"
else: else:
raise NotImplemented(size) raise NotImplemented(size)
@ -133,7 +133,7 @@ def blocks(rows):
raw_pad = (offset - last_offset) << 16 raw_pad = (offset - last_offset) << 16
yield f"{type} _pad{reserved_num}[{hex(raw_pad)} - (sizeof (struct {last_block.lower()}_reg))];" yield f"{type} _pad{reserved_num}[{hex(raw_pad)} - (sizeof (struct {last_block.lower()}_reg))];"
reserved_num += 1 reserved_num += 1
yield f"{block.lower()}_reg {block};" yield f"struct {block.lower()}_reg {block};"
last_offset = offset last_offset = offset
last_block = block last_block = block
yield "};" yield "};"
@ -142,12 +142,14 @@ def blocks(rows):
yield f"static_assert((offsetof (struct sh7091_reg, {block})) == {hex(offset << 16)});" yield f"static_assert((offsetof (struct sh7091_reg, {block})) == {hex(offset << 16)});"
yield "" yield ""
yield "extern sh7091_reg SH7091;" yield 'extern struct sh7091_reg SH7091 __asm("SH7091");'
def headers(): def headers():
yield "#include <stdint.h>" yield "#include <stdint.h>"
yield "#include <stddef.h>" yield "#include <stddef.h>"
yield "" yield ""
yield '#include "type.h"'
yield ""
if __name__ == "__main__": if __name__ == "__main__":
input_file = sys.argv[1] input_file = sys.argv[1]

402
sh7091.h
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@ -1,24 +1,26 @@
#include <cstdint> #include <stdint.h>
#include <cstddef> #include <stddef.h>
#include "type.h"
struct ccn_reg { struct ccn_reg {
uint32_t PTEH; /* Page table entry high register */ reg32 PTEH; /* Page table entry high register */
uint32_t PTEL; /* Page table entry low register */ reg32 PTEL; /* Page table entry low register */
uint32_t TTB; /* Translation table base register */ reg32 TTB; /* Translation table base register */
uint32_t TEA; /* TLB exception address register */ reg32 TEA; /* TLB exception address register */
uint32_t MMUCR; /* MMU control register */ reg32 MMUCR; /* MMU control register */
uint8_t BASRA; /* Break ASID register A */ reg8 BASRA; /* Break ASID register A */
uint8_t _pad0[3]; reg8 _pad0[3];
uint8_t BASRB; /* Break ASID register B */ reg8 BASRB; /* Break ASID register B */
uint8_t _pad1[3]; reg8 _pad1[3];
uint32_t CCR; /* Cache control register */ reg32 CCR; /* Cache control register */
uint32_t TRA; /* TRAPA exception register */ reg32 TRA; /* TRAPA exception register */
uint32_t EXPEVT; /* Exception event register */ reg32 EXPEVT; /* Exception event register */
uint32_t INTEVT; /* Interrupt event register */ reg32 INTEVT; /* Interrupt event register */
uint8_t _pad2[8]; reg8 _pad2[8];
uint32_t PTEA; /* Page table entry assistance register */ reg32 PTEA; /* Page table entry assistance register */
uint32_t QACR0; /* Queue address control register 0 */ reg32 QACR0; /* Queue address control register 0 */
uint32_t QACR1; /* Queue address control register 1 */ reg32 QACR1; /* Queue address control register 1 */
}; };
static_assert((offsetof (struct ccn_reg, PTEH)) == 0x0); static_assert((offsetof (struct ccn_reg, PTEH)) == 0x0);
@ -37,19 +39,19 @@ static_assert((offsetof (struct ccn_reg, QACR0)) == 0x38);
static_assert((offsetof (struct ccn_reg, QACR1)) == 0x3c); static_assert((offsetof (struct ccn_reg, QACR1)) == 0x3c);
struct ubc_reg { struct ubc_reg {
uint32_t BARA; /* Break address register A */ reg32 BARA; /* Break address register A */
uint8_t BAMRA; /* Break address mask register A */ reg8 BAMRA; /* Break address mask register A */
uint8_t _pad0[3]; reg8 _pad0[3];
uint16_t BBRA; /* Break bus cycle register A */ reg16 BBRA; /* Break bus cycle register A */
uint8_t _pad1[2]; reg8 _pad1[2];
uint32_t BARB; /* Break address register B */ reg32 BARB; /* Break address register B */
uint8_t BAMRB; /* Break address mask register B */ reg8 BAMRB; /* Break address mask register B */
uint8_t _pad2[3]; reg8 _pad2[3];
uint16_t BBRB; /* Break bus cycle register B */ reg16 BBRB; /* Break bus cycle register B */
uint8_t _pad3[2]; reg8 _pad3[2];
uint32_t BDRB; /* Break data register B */ reg32 BDRB; /* Break data register B */
uint32_t BDMRB; /* Break data mask register B */ reg32 BDMRB; /* Break data mask register B */
uint16_t BRCR; /* Break control register */ reg16 BRCR; /* Break control register */
}; };
static_assert((offsetof (struct ubc_reg, BARA)) == 0x0); static_assert((offsetof (struct ubc_reg, BARA)) == 0x0);
@ -63,34 +65,34 @@ static_assert((offsetof (struct ubc_reg, BDMRB)) == 0x1c);
static_assert((offsetof (struct ubc_reg, BRCR)) == 0x20); static_assert((offsetof (struct ubc_reg, BRCR)) == 0x20);
struct bsc_reg { struct bsc_reg {
uint32_t BCR1; /* Bus control register 1 */ reg32 BCR1; /* Bus control register 1 */
uint16_t BCR2; /* Bus control register 2 */ reg16 BCR2; /* Bus control register 2 */
uint8_t _pad0[2]; reg8 _pad0[2];
uint32_t WCR1; /* Wait state control register 1 */ reg32 WCR1; /* Wait state control register 1 */
uint32_t WCR2; /* Wait state control register 2 */ reg32 WCR2; /* Wait state control register 2 */
uint32_t WCR3; /* Wait state control register 3 */ reg32 WCR3; /* Wait state control register 3 */
uint32_t MCR; /* Memory control register */ reg32 MCR; /* Memory control register */
uint16_t PCR; /* PCMCIA control register */ reg16 PCR; /* PCMCIA control register */
uint8_t _pad1[2]; reg8 _pad1[2];
uint16_t RTCSR; /* Refresh timer control/status register */ reg16 RTCSR; /* Refresh timer control/status register */
uint8_t _pad2[2]; reg8 _pad2[2];
uint16_t RTCNT; /* Refresh timer counter */ reg16 RTCNT; /* Refresh timer counter */
uint8_t _pad3[2]; reg8 _pad3[2];
uint16_t RTCOR; /* Refresh timer constant counter */ reg16 RTCOR; /* Refresh timer constant counter */
uint8_t _pad4[2]; reg8 _pad4[2];
uint16_t RFCR; /* Refresh count register */ reg16 RFCR; /* Refresh count register */
uint8_t _pad5[2]; reg8 _pad5[2];
uint32_t PCTRA; /* Port control register A */ reg32 PCTRA; /* Port control register A */
uint16_t PDTRA; /* Port data register A */ reg16 PDTRA; /* Port data register A */
uint8_t _pad6[14]; reg8 _pad6[14];
uint32_t PCTRB; /* Port control register B */ reg32 PCTRB; /* Port control register B */
uint16_t PDTRB; /* Port data register B */ reg16 PDTRB; /* Port data register B */
uint8_t _pad7[2]; reg8 _pad7[2];
uint16_t GPIOIC; /* GPIO interrupt control register */ reg16 GPIOIC; /* GPIO interrupt control register */
uint8_t _pad8[1048502]; reg8 _pad8[1048502];
uint8_t SDMR2[65536]; /* Synchronous DRAM mode registers */ reg8 SDMR2[65536]; /* Synchronous DRAM mode registers */
uint8_t _pad9[196608]; reg8 _pad9[196608];
uint8_t SDMR3[65536]; /* Synchronous DRAM mode registers */ reg8 SDMR3[65536]; /* Synchronous DRAM mode registers */
}; };
static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0); static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0);
@ -113,23 +115,23 @@ static_assert((offsetof (struct bsc_reg, SDMR2)) == 0x100000);
static_assert((offsetof (struct bsc_reg, SDMR3)) == 0x140000); static_assert((offsetof (struct bsc_reg, SDMR3)) == 0x140000);
struct dmac_reg { struct dmac_reg {
uint32_t SAR0; /* DMA source address register 0 */ reg32 SAR0; /* DMA source address register 0 */
uint32_t DAR0; /* DMA destination address register 0 */ reg32 DAR0; /* DMA destination address register 0 */
uint32_t DMATCR0; /* DMA transfer count register 0 */ reg32 DMATCR0; /* DMA transfer count register 0 */
uint32_t CHCR0; /* DMA control register 0 */ reg32 CHCR0; /* DMA control register 0 */
uint32_t SAR1; /* DMA source address register 1 */ reg32 SAR1; /* DMA source address register 1 */
uint32_t DAR1; /* DMA destination address register 1 */ reg32 DAR1; /* DMA destination address register 1 */
uint32_t DMATCR1; /* DMA transfer count register 1 */ reg32 DMATCR1; /* DMA transfer count register 1 */
uint32_t CHCR1; /* DMA control register 1 */ reg32 CHCR1; /* DMA control register 1 */
uint32_t SAR2; /* DMA source address register 2 */ reg32 SAR2; /* DMA source address register 2 */
uint32_t DAR2; /* DMA destination address register 2 */ reg32 DAR2; /* DMA destination address register 2 */
uint32_t DMATCR2; /* DMA transfer count register 2 */ reg32 DMATCR2; /* DMA transfer count register 2 */
uint32_t CHCR2; /* DMA control register 2 */ reg32 CHCR2; /* DMA control register 2 */
uint32_t SAR3; /* DMA source address register 3 */ reg32 SAR3; /* DMA source address register 3 */
uint32_t DAR3; /* DMA destination address register 3 */ reg32 DAR3; /* DMA destination address register 3 */
uint32_t DMATCR3; /* DMA transfer count register 3 */ reg32 DMATCR3; /* DMA transfer count register 3 */
uint32_t CHCR3; /* DMA control register 3 */ reg32 CHCR3; /* DMA control register 3 */
uint32_t DMAOR; /* DMA operation register */ reg32 DMAOR; /* DMA operation register */
}; };
static_assert((offsetof (struct dmac_reg, SAR0)) == 0x0); static_assert((offsetof (struct dmac_reg, SAR0)) == 0x0);
@ -151,15 +153,15 @@ static_assert((offsetof (struct dmac_reg, CHCR3)) == 0x3c);
static_assert((offsetof (struct dmac_reg, DMAOR)) == 0x40); static_assert((offsetof (struct dmac_reg, DMAOR)) == 0x40);
struct cpg_reg { struct cpg_reg {
uint16_t FRQCR; /* Frequency control register */ reg16 FRQCR; /* Frequency control register */
uint8_t _pad0[2]; reg8 _pad0[2];
uint8_t STBCR; /* Standby control register */ reg8 STBCR; /* Standby control register */
uint8_t _pad1[3]; reg8 _pad1[3];
uint16_t WTCNT; /* Watchdog timer counter */ reg16 WTCNT; /* Watchdog timer counter */
uint8_t _pad2[2]; reg8 _pad2[2];
uint16_t WTCSR; /* Watchdog timer control/status register */ reg16 WTCSR; /* Watchdog timer control/status register */
uint8_t _pad3[2]; reg8 _pad3[2];
uint8_t STBCR2; /* Standby control register 2 */ reg8 STBCR2; /* Standby control register 2 */
}; };
static_assert((offsetof (struct cpg_reg, FRQCR)) == 0x0); static_assert((offsetof (struct cpg_reg, FRQCR)) == 0x0);
@ -169,37 +171,37 @@ static_assert((offsetof (struct cpg_reg, WTCSR)) == 0xc);
static_assert((offsetof (struct cpg_reg, STBCR2)) == 0x10); static_assert((offsetof (struct cpg_reg, STBCR2)) == 0x10);
struct rtc_reg { struct rtc_reg {
uint8_t R64CNT; /* 64 Hz counter */ reg8 R64CNT; /* 64 Hz counter */
uint8_t _pad0[3]; reg8 _pad0[3];
uint8_t RSECCNT; /* Second counter */ reg8 RSECCNT; /* Second counter */
uint8_t _pad1[3]; reg8 _pad1[3];
uint8_t RMINCNT; /* Minute counter */ reg8 RMINCNT; /* Minute counter */
uint8_t _pad2[3]; reg8 _pad2[3];
uint8_t RHRCNT; /* Hour counter */ reg8 RHRCNT; /* Hour counter */
uint8_t _pad3[3]; reg8 _pad3[3];
uint8_t RWKCNT; /* Day-of-week counter */ reg8 RWKCNT; /* Day-of-week counter */
uint8_t _pad4[3]; reg8 _pad4[3];
uint8_t RDAYCNT; /* Day counter */ reg8 RDAYCNT; /* Day counter */
uint8_t _pad5[3]; reg8 _pad5[3];
uint8_t RMONCNT; /* Month counter */ reg8 RMONCNT; /* Month counter */
uint8_t _pad6[3]; reg8 _pad6[3];
uint16_t RYRCNT; /* Year counter */ reg16 RYRCNT; /* Year counter */
uint8_t _pad7[2]; reg8 _pad7[2];
uint8_t RSECAR; /* Second alarm register */ reg8 RSECAR; /* Second alarm register */
uint8_t _pad8[3]; reg8 _pad8[3];
uint8_t RMINAR; /* Minute alarm register */ reg8 RMINAR; /* Minute alarm register */
uint8_t _pad9[3]; reg8 _pad9[3];
uint8_t RHRAR; /* Hour alarm register */ reg8 RHRAR; /* Hour alarm register */
uint8_t _pad10[3]; reg8 _pad10[3];
uint8_t RWKAR; /* Day-of-week alarm register */ reg8 RWKAR; /* Day-of-week alarm register */
uint8_t _pad11[3]; reg8 _pad11[3];
uint8_t RDAYAR; /* Day alarm register */ reg8 RDAYAR; /* Day alarm register */
uint8_t _pad12[3]; reg8 _pad12[3];
uint8_t RMONAR; /* Month alarm register */ reg8 RMONAR; /* Month alarm register */
uint8_t _pad13[3]; reg8 _pad13[3];
uint8_t RCR1; /* RTC control register 1 */ reg8 RCR1; /* RTC control register 1 */
uint8_t _pad14[3]; reg8 _pad14[3];
uint8_t RCR2; /* RTC control register 2 */ reg8 RCR2; /* RTC control register 2 */
}; };
static_assert((offsetof (struct rtc_reg, R64CNT)) == 0x0); static_assert((offsetof (struct rtc_reg, R64CNT)) == 0x0);
@ -220,13 +222,13 @@ static_assert((offsetof (struct rtc_reg, RCR1)) == 0x38);
static_assert((offsetof (struct rtc_reg, RCR2)) == 0x3c); static_assert((offsetof (struct rtc_reg, RCR2)) == 0x3c);
struct intc_reg { struct intc_reg {
uint16_t ICR; /* Interrupt control register */ reg16 ICR; /* Interrupt control register */
uint8_t _pad0[2]; reg8 _pad0[2];
uint16_t IPRA; /* Interrupt priority register A */ reg16 IPRA; /* Interrupt priority register A */
uint8_t _pad1[2]; reg8 _pad1[2];
uint16_t IPRB; /* Interrupt priority register B */ reg16 IPRB; /* Interrupt priority register B */
uint8_t _pad2[2]; reg8 _pad2[2];
uint16_t IPRC; /* Interrupt priority register C */ reg16 IPRC; /* Interrupt priority register C */
}; };
static_assert((offsetof (struct intc_reg, ICR)) == 0x0); static_assert((offsetof (struct intc_reg, ICR)) == 0x0);
@ -235,23 +237,23 @@ static_assert((offsetof (struct intc_reg, IPRB)) == 0x8);
static_assert((offsetof (struct intc_reg, IPRC)) == 0xc); static_assert((offsetof (struct intc_reg, IPRC)) == 0xc);
struct tmu_reg { struct tmu_reg {
uint8_t TOCR; /* Timer output control register */ reg8 TOCR; /* Timer output control register */
uint8_t _pad0[3]; reg8 _pad0[3];
uint8_t TSTR; /* Timer start register */ reg8 TSTR; /* Timer start register */
uint8_t _pad1[3]; reg8 _pad1[3];
uint32_t TCOR0; /* Timer constant register 0 */ reg32 TCOR0; /* Timer constant register 0 */
uint32_t TCNT0; /* Timer counter 0 */ reg32 TCNT0; /* Timer counter 0 */
uint16_t TCR0; /* Timer control register 0 */ reg16 TCR0; /* Timer control register 0 */
uint8_t _pad2[2]; reg8 _pad2[2];
uint32_t TCOR1; /* Timer constant register 1 */ reg32 TCOR1; /* Timer constant register 1 */
uint32_t TCNT1; /* Timer counter 1 */ reg32 TCNT1; /* Timer counter 1 */
uint16_t TCR1; /* Timer control register 1 */ reg16 TCR1; /* Timer control register 1 */
uint8_t _pad3[2]; reg8 _pad3[2];
uint32_t TCOR2; /* Timer constant register 2 */ reg32 TCOR2; /* Timer constant register 2 */
uint32_t TCNT2; /* Timer counter 2 */ reg32 TCNT2; /* Timer counter 2 */
uint16_t TCR2; /* Timer control register 2 */ reg16 TCR2; /* Timer control register 2 */
uint8_t _pad4[2]; reg8 _pad4[2];
uint32_t TCPR2; /* Timer input capture register 2 */ reg32 TCPR2; /* Timer input capture register 2 */
}; };
static_assert((offsetof (struct tmu_reg, TOCR)) == 0x0); static_assert((offsetof (struct tmu_reg, TOCR)) == 0x0);
@ -268,21 +270,21 @@ static_assert((offsetof (struct tmu_reg, TCR2)) == 0x28);
static_assert((offsetof (struct tmu_reg, TCPR2)) == 0x2c); static_assert((offsetof (struct tmu_reg, TCPR2)) == 0x2c);
struct sci_reg { struct sci_reg {
uint8_t SCSMR1; /* Serial mode register 1 */ reg8 SCSMR1; /* Serial mode register 1 */
uint8_t _pad0[3]; reg8 _pad0[3];
uint8_t SCBRR1; /* Bit rate register 1 */ reg8 SCBRR1; /* Bit rate register 1 */
uint8_t _pad1[3]; reg8 _pad1[3];
uint8_t SCSCR1; /* Serial control register 1 */ reg8 SCSCR1; /* Serial control register 1 */
uint8_t _pad2[3]; reg8 _pad2[3];
uint8_t SCTDR1; /* Transmit data register 1 */ reg8 SCTDR1; /* Transmit data register 1 */
uint8_t _pad3[3]; reg8 _pad3[3];
uint8_t SCSSR1; /* Serial status register 1 */ reg8 SCSSR1; /* Serial status register 1 */
uint8_t _pad4[3]; reg8 _pad4[3];
uint8_t SCRDR1; /* Receive data register 1 */ reg8 SCRDR1; /* Receive data register 1 */
uint8_t _pad5[3]; reg8 _pad5[3];
uint8_t SCSCMR1; /* Smart card mode register 1 */ reg8 SCSCMR1; /* Smart card mode register 1 */
uint8_t _pad6[3]; reg8 _pad6[3];
uint8_t SCSPTR1; /* Serial port register */ reg8 SCSPTR1; /* Serial port register */
}; };
static_assert((offsetof (struct sci_reg, SCSMR1)) == 0x0); static_assert((offsetof (struct sci_reg, SCSMR1)) == 0x0);
@ -295,25 +297,25 @@ static_assert((offsetof (struct sci_reg, SCSCMR1)) == 0x18);
static_assert((offsetof (struct sci_reg, SCSPTR1)) == 0x1c); static_assert((offsetof (struct sci_reg, SCSPTR1)) == 0x1c);
struct scif_reg { struct scif_reg {
uint16_t SCSMR2; /* Serial mode register 2 */ reg16 SCSMR2; /* Serial mode register 2 */
uint8_t _pad0[2]; reg8 _pad0[2];
uint8_t SCBRR2; /* Bit rate register 2 */ reg8 SCBRR2; /* Bit rate register 2 */
uint8_t _pad1[3]; reg8 _pad1[3];
uint16_t SCSCR2; /* Serial control register 2 */ reg16 SCSCR2; /* Serial control register 2 */
uint8_t _pad2[2]; reg8 _pad2[2];
uint8_t SCFTDR2; /* Transmit FIFO data register 2 */ reg8 SCFTDR2; /* Transmit FIFO data register 2 */
uint8_t _pad3[3]; reg8 _pad3[3];
uint16_t SCFSR2; /* Serial status register 2 */ reg16 SCFSR2; /* Serial status register 2 */
uint8_t _pad4[2]; reg8 _pad4[2];
uint8_t SCFRDR2; /* Receive FIFO data register 2 */ reg8 SCFRDR2; /* Receive FIFO data register 2 */
uint8_t _pad5[3]; reg8 _pad5[3];
uint16_t SCFCR2; /* FIFO control register */ reg16 SCFCR2; /* FIFO control register */
uint8_t _pad6[2]; reg8 _pad6[2];
uint16_t SCFDR2; /* FIFO data count register */ reg16 SCFDR2; /* FIFO data count register */
uint8_t _pad7[2]; reg8 _pad7[2];
uint16_t SCSPTR2; /* Serial port register 2 */ reg16 SCSPTR2; /* Serial port register 2 */
uint8_t _pad8[2]; reg8 _pad8[2];
uint16_t SCLSR2; /* Line status register 2 */ reg16 SCLSR2; /* Line status register 2 */
}; };
static_assert((offsetof (struct scif_reg, SCSMR2)) == 0x0); static_assert((offsetof (struct scif_reg, SCSMR2)) == 0x0);
@ -328,36 +330,36 @@ static_assert((offsetof (struct scif_reg, SCSPTR2)) == 0x20);
static_assert((offsetof (struct scif_reg, SCLSR2)) == 0x24); static_assert((offsetof (struct scif_reg, SCLSR2)) == 0x24);
struct udi_reg { struct udi_reg {
uint16_t SDIR; /* Instruction register */ reg16 SDIR; /* Instruction register */
uint8_t _pad0[6]; reg8 _pad0[6];
uint32_t SDDR; /* Data register */ reg32 SDDR; /* Data register */
}; };
static_assert((offsetof (struct udi_reg, SDIR)) == 0x0); static_assert((offsetof (struct udi_reg, SDIR)) == 0x0);
static_assert((offsetof (struct udi_reg, SDDR)) == 0x8); static_assert((offsetof (struct udi_reg, SDDR)) == 0x8);
struct sh7091_reg { struct sh7091_reg {
ccn_reg CCN; struct ccn_reg CCN;
uint8_t _pad0[0x200000 - (sizeof (struct ccn_reg))]; reg8 _pad0[0x200000 - (sizeof (struct ccn_reg))];
ubc_reg UBC; struct ubc_reg UBC;
uint8_t _pad1[0x600000 - (sizeof (struct ubc_reg))]; reg8 _pad1[0x600000 - (sizeof (struct ubc_reg))];
bsc_reg BSC; struct bsc_reg BSC;
uint8_t _pad2[0x200000 - (sizeof (struct bsc_reg))]; reg8 _pad2[0x200000 - (sizeof (struct bsc_reg))];
dmac_reg DMAC; struct dmac_reg DMAC;
uint8_t _pad3[0x200000 - (sizeof (struct dmac_reg))]; reg8 _pad3[0x200000 - (sizeof (struct dmac_reg))];
cpg_reg CPG; struct cpg_reg CPG;
uint8_t _pad4[0x80000 - (sizeof (struct cpg_reg))]; reg8 _pad4[0x80000 - (sizeof (struct cpg_reg))];
rtc_reg RTC; struct rtc_reg RTC;
uint8_t _pad5[0x80000 - (sizeof (struct rtc_reg))]; reg8 _pad5[0x80000 - (sizeof (struct rtc_reg))];
intc_reg INTC; struct intc_reg INTC;
uint8_t _pad6[0x80000 - (sizeof (struct intc_reg))]; reg8 _pad6[0x80000 - (sizeof (struct intc_reg))];
tmu_reg TMU; struct tmu_reg TMU;
uint8_t _pad7[0x80000 - (sizeof (struct tmu_reg))]; reg8 _pad7[0x80000 - (sizeof (struct tmu_reg))];
sci_reg SCI; struct sci_reg SCI;
uint8_t _pad8[0x80000 - (sizeof (struct sci_reg))]; reg8 _pad8[0x80000 - (sizeof (struct sci_reg))];
scif_reg SCIF; struct scif_reg SCIF;
uint8_t _pad9[0x80000 - (sizeof (struct scif_reg))]; reg8 _pad9[0x80000 - (sizeof (struct scif_reg))];
udi_reg UDI; struct udi_reg UDI;
}; };
static_assert((offsetof (struct sh7091_reg, CCN)) == 0x0); static_assert((offsetof (struct sh7091_reg, CCN)) == 0x0);
@ -372,5 +374,5 @@ static_assert((offsetof (struct sh7091_reg, SCI)) == 0xe00000);
static_assert((offsetof (struct sh7091_reg, SCIF)) == 0xe80000); static_assert((offsetof (struct sh7091_reg, SCIF)) == 0xe80000);
static_assert((offsetof (struct sh7091_reg, UDI)) == 0xf00000); static_assert((offsetof (struct sh7091_reg, UDI)) == 0xf00000);
extern sh7091_reg SH7091; extern struct sh7091_reg SH7091 __asm("SH7091");

9
sh7091_bits.h Normal file
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@ -0,0 +1,9 @@
#define CCR__IIX (1 << 15)
#define CCR__ICI (1 << 11)
#define CCR__ICE (1 << 8)
#define CCR__OIX (1 << 7)
#define CCR__ORA (1 << 5)
#define CCR__OCI (1 << 4)
#define CCR__CB (1 << 2)
#define CCR__WT (1 << 1)
#define CCR__OCE (1 << 0)

24
start.s Normal file
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@ -0,0 +1,24 @@
.section .text.start
.global _start
_start:
/* set stack pointer */
mov.l p1ram_end_ptr,r15
/* mask all interrupts */
mov.l imask_all,r0
stc sr,r1
or r1,r0
ldc r0,sr
/* jump to main */
mov.l main_ptr,r0
jmp @r0
nop
.align 4
p1ram_end_ptr:
.long __p1ram_end
imask_all:
.long 0xf0
main_ptr:
.long _main