diff --git a/regs/isp_tsp.csv b/regs/isp_tsp.csv
index 0859693..11e23bf 100644
--- a/regs/isp_tsp.csv
+++ b/regs/isp_tsp.csv
@@ -106,21 +106,21 @@
 ,,,,,,
 "texture_control_word",,30,"vq_compressed",1,,
 ,,,,,,
-"tsp_instruction_word","pixel_format","29-27",1555,0,,
-"tsp_instruction_word","pixel_format","29-27",565,1,,
-"tsp_instruction_word","pixel_format","29-27",4444,2,,
-"tsp_instruction_word","pixel_format","29-27","yuv422",3,,
-"tsp_instruction_word","pixel_format","29-27","bump_map",4,,
-"tsp_instruction_word","pixel_format","29-27","4bpp_palette",5,,
-"tsp_instruction_word","pixel_format","29-27","8bpp_palette",6,,
+"texture_control_word","pixel_format","29-27",1555,0,,
+"texture_control_word","pixel_format","29-27",565,1,,
+"texture_control_word","pixel_format","29-27",4444,2,,
+"texture_control_word","pixel_format","29-27","yuv422",3,,
+"texture_control_word","pixel_format","29-27","bump_map",4,,
+"texture_control_word","pixel_format","29-27","4bpp_palette",5,,
+"texture_control_word","pixel_format","29-27","8bpp_palette",6,,
 ,,,,,,
-"tsp_instruction_word","scan_order",26,"twiddled",0,,
-"tsp_instruction_word","scan_order",26,"non_twiddled",1,,
+"texture_control_word","scan_order",26,"twiddled",0,,
+"texture_control_word","scan_order",26,"non_twiddled",1,,
 ,,,,,,
-"tsp_instruction_word",,"26-21","palette_selector4",,"0x3f",
+"texture_control_word",,"26-21","palette_selector4",,"0x3f",
 ,,,,,,
-"tsp_instruction_word",,"26-25","palette_selector8",,"0x3",
+"texture_control_word",,"26-25","palette_selector8",,"0x3",
 ,,,,,,
-"tsp_instruction_word",,25,"stride_select",,,
+"texture_control_word",,25,"stride_select",,,
 ,,,,,,
-"tsp_instruction_word",,"20-0","texture_address",,"0x1fffff",
+"texture_control_word",,"20-0","texture_address",,"0x1fffff",
diff --git a/regs/isp_tsp.ods b/regs/isp_tsp.ods
index ccf73e1..a47ca22 100644
Binary files a/regs/isp_tsp.ods and b/regs/isp_tsp.ods differ
diff --git a/regs/systembus.csv b/regs/systembus.csv
index 4ed3745..6e8983e 100644
--- a/regs/systembus.csv
+++ b/regs/systembus.csv
@@ -1,49 +1,49 @@
 "block","address","size","name","r/w","description"
-"SYSTEM","000","4","C2DSTAT","RW","CH2-DMA destination address"
-"SYSTEM","004","4","C2DLEN","RW","CH2-DMA length"
-"SYSTEM","008","4","C2DST","RW","CH2-DMA start"
+"SYSTEMBUS","000","4","C2DSTAT","RW","CH2-DMA destination address"
+"SYSTEMBUS","004","4","C2DLEN","RW","CH2-DMA length"
+"SYSTEMBUS","008","4","C2DST","RW","CH2-DMA start"
 ,,,,,
-"SYSTEM","010","4","SDSTAW","RW","Sort-DMA start link table address"
-"SYSTEM","014","4","SDBAAW","RW","Sort-DMA link base address"
-"SYSTEM","018","4","SDWLT","RW","Sort-DMA link address bit width"
-"SYSTEM","01c","4","SDLAS","RW","Sort-DMA link address shift control"
-"SYSTEM","020","4","SDST","RW","Sort-DMA start"
+"SYSTEMBUS","010","4","SDSTAW","RW","Sort-DMA start link table address"
+"SYSTEMBUS","014","4","SDBAAW","RW","Sort-DMA link base address"
+"SYSTEMBUS","018","4","SDWLT","RW","Sort-DMA link address bit width"
+"SYSTEMBUS","01c","4","SDLAS","RW","Sort-DMA link address shift control"
+"SYSTEMBUS","020","4","SDST","RW","Sort-DMA start"
 ,,,,,
-"SYSTEM","040","4","DBREQM","RW","DBREQ# signal mask control"
-"SYSTEM","044","4","BAVLWC","RW","BAVL# signal wait count"
-"SYSTEM","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
-"SYSTEM","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
+"SYSTEMBUS","040","4","DBREQM","RW","DBREQ# signal mask control"
+"SYSTEMBUS","044","4","BAVLWC","RW","BAVL# signal wait count"
+"SYSTEMBUS","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
+"SYSTEMBUS","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
 ,,,,,
-"SYSTEM","080","4","TFREM","R","TA FIFO remaining amount"
-"SYSTEM","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
-"SYSTEM","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
-"SYSTEM","08c","4","FFST","R","FIFO status"
-"SYSTEM","090","4","SFRES","W","System reset"
+"SYSTEMBUS","080","4","TFREM","R","TA FIFO remaining amount"
+"SYSTEMBUS","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
+"SYSTEMBUS","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
+"SYSTEMBUS","08c","4","FFST","R","FIFO status"
+"SYSTEMBUS","090","4","SFRES","W","System reset"
 ,,,,,
-"SYSTEM","09c","4","SBREV","R","System bus revision number"
-"SYSTEM","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
+"SYSTEMBUS","09c","4","SBREV","R","System bus revision number"
+"SYSTEMBUS","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
 ,,,,,
-"SYSTEM","100","4","ISTNRM","RW","Normal interrupt status"
-"SYSTEM","104","4","ISTEXT","R","External interrupt status"
-"SYSTEM","108","4","ISTERR","RW","Error interrupt status"
+"SYSTEMBUS","100","4","ISTNRM","RW","Normal interrupt status"
+"SYSTEMBUS","104","4","ISTEXT","R","External interrupt status"
+"SYSTEMBUS","108","4","ISTERR","RW","Error interrupt status"
 ,,,,,
-"SYSTEM","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
-"SYSTEM","114","4","IML2EXT","RW","Level 2 external interrupt mask"
-"SYSTEM","118","4","IML2ERR","RW","Level 2 error interrupt mask"
+"SYSTEMBUS","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
+"SYSTEMBUS","114","4","IML2EXT","RW","Level 2 external interrupt mask"
+"SYSTEMBUS","118","4","IML2ERR","RW","Level 2 error interrupt mask"
 ,,,,,
-"SYSTEM","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
-"SYSTEM","124","4","IML4EXT","RW","Level 4 external interrupt mask"
-"SYSTEM","128","4","IML4ERR","RW","Level 4 error interrupt mask"
+"SYSTEMBUS","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
+"SYSTEMBUS","124","4","IML4EXT","RW","Level 4 external interrupt mask"
+"SYSTEMBUS","128","4","IML4ERR","RW","Level 4 error interrupt mask"
 ,,,,,
-"SYSTEM","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
-"SYSTEM","134","4","IML6EXT","RW","Level 6 external interrupt mask"
-"SYSTEM","138","4","IML6ERR","RW","Level 6 error interrupt mask"
+"SYSTEMBUS","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
+"SYSTEMBUS","134","4","IML6EXT","RW","Level 6 external interrupt mask"
+"SYSTEMBUS","138","4","IML6ERR","RW","Level 6 error interrupt mask"
 ,,,,,
-"SYSTEM","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
-"SYSTEM","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
+"SYSTEMBUS","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
+"SYSTEMBUS","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
 ,,,,,
-"SYSTEM","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
-"SYSTEM","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
+"SYSTEMBUS","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
+"SYSTEMBUS","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
 ,,,,,
 "MAPLE_IF","04","4","MDSTAR","RW","Maple-DMA command table address"
 ,,,,,
diff --git a/regs/systembus.ods b/regs/systembus.ods
index a486842..a98930b 100644
Binary files a/regs/systembus.ods and b/regs/systembus.ods differ