holly: add core_param_init, ta_fifo_texture_memory_transfer

holly/core.cpp

@@ -53,6 +53,29 @@ void core_init()
 		       | fpu_param_cfg::pointer_first_burst_size(7); // half of pointer burst size(?)
 }
 
+void core_param_init(uint32_t region_array_start,
+                     uint32_t isp_tsp_parameters_start,
+                     uint32_t background_start,
+                     uint32_t framebuffer_width)
+{
+  holly.REGION_BASE = region_array_start;
+  holly.PARAM_BASE = isp_tsp_parameters_start;
+
+  uint32_t background_offset = background_start - isp_tsp_parameters_start;
+
+  holly.ISP_BACKGND_T
+    = isp_backgnd_t::tag_address(background_offset / 4)
+    | isp_backgnd_t::tag_offset(0)
+    | isp_backgnd_t::skip(1);
+  holly.ISP_BACKGND_D = _i(1.f/100000.f);
+
+  holly.FB_W_CTRL
+    = fb_w_ctrl::fb_packmode::_565_rgb_16bit;
+
+  const int bytes_per_pixel = 2;
+  holly.FB_W_LINESTRIDE = (framebuffer_width * bytes_per_pixel) / 8;
+}
+
 void core_start_render(uint32_t frame_address,
 		       uint32_t frame_width      // in pixels
 		       )

holly/core.hpp

@@ -4,6 +4,11 @@
 
 void core_init();
 
+void core_param_init(uint32_t region_array_start,
+                     uint32_t isp_tsp_parameters_start,
+                     uint32_t background_start,
+                     uint32_t framebuffer_width);
+
 void core_start_render(uint32_t frame_address,
 		       uint32_t frame_width); // in pixels
 

holly/ta_fifo_texture_memory_transfer.hpp

@@ -0,0 +1,68 @@
+#pragma once
+
+#include "sh7091/store_queue.hpp"
+#include "memorymap.hpp"
+
+namespace ta_fifo_texture_memory_transfer {
+
+  static inline void copy(void * out_addr,
+                          const void * src,
+                          int length)
+  {
+    uint32_t out = reinterpret_cast<uint32_t>(out_addr);
+    sh7091.CCN.QACR0 = ((out >> 24) & 0b11100);
+    sh7091.CCN.QACR1 = ((out >> 24) & 0b11100);
+
+    volatile uint32_t * base = &store_queue[(out & 0x03ffffe0) / 4];
+    const uint32_t * src32 = reinterpret_cast<const uint32_t *>(src);
+
+    length = (length + 31) & ~31; // round up to nearest multiple of 32
+    while (length > 0) {
+      base[0] = src32[0];
+      base[1] = src32[1];
+      base[2] = src32[2];
+      base[3] = src32[3];
+      base[4] = src32[4];
+      base[5] = src32[5];
+      base[6] = src32[6];
+      base[7] = src32[7];
+      asm volatile ("pref @%0"
+                    :                // output
+                    : "r" (&base[0]) // input
+                    : "memory");
+      length -= 32;
+      base += 8;
+      src32 += 8;
+    }
+  }
+
+
+  static inline void zeroize(void * out_addr,
+                             int length,
+                             const uint32_t value)
+  {
+    uint32_t out = reinterpret_cast<uint32_t>(out_addr);
+    sh7091.CCN.QACR0 = ((out >> 24) & 0b11100);
+    sh7091.CCN.QACR1 = ((out >> 24) & 0b11100);
+
+    volatile uint32_t * base = &store_queue[(out & 0x03ffffe0) / 4];
+
+    length = (length + 31) & ~31; // round up to nearest multiple of 32
+    while (length > 0) {
+      base[0] = value;
+      base[1] = value;
+      base[2] = value;
+      base[3] = value;
+      base[4] = value;
+      base[5] = value;
+      base[6] = value;
+      base[7] = value;
+      asm volatile ("pref @%0"
+                    :                // output
+                    : "r" (&base[0]) // input
+                    : "memory");
+      length -= 32;
+      base += 8;
+    }
+  }
+}