#define C2DST__STATUS (1 << 0)

#define CD2LEN__LENGTH(n) (((n) & 0xffffe0) << 0)

#define C2DSTAT__ADDRESS(n) ((((n) & 0x13ffffe0) | 0x10000000) << 0)

#define ISTNRM__END_OF_TRANSFERRING_PUNCH_THROUGH_LIST (1 << 21)
#define ISTNRM__END_OF_DMA_SORT_DMA (1 << 20)
#define ISTNRM__END_OF_DMA_CH2_DMA (1 << 19)
#define ISTNRM__END_OF_DMA_DEV_DMA (1 << 18)
#define ISTNRM__END_OF_DMA_EXT_DMA2 (1 << 17)
#define ISTNRM__END_OF_DMA_EXT_DMA1 (1 << 16)
#define ISTNRM__END_OF_DMA_AICA_DMA (1 << 15)
#define ISTNRM__END_OF_DMA_GD_DMA (1 << 14)
#define ISTNRM__MAPLE_V_BLANK_OVER_INTERRUPT (1 << 13)
#define ISTNRM__END_OF_DMA_MAPLE_DMA (1 << 12)
#define ISTNRM__END_OF_DMA_PVR_DMA (1 << 11)
#define ISTNRM__END_OF_TRANSFERRING_TRANSLUCENT_MODIFIER_VOLUME_LIST (1 << 10)
#define ISTNRM__END_OF_TRANSFERRING_TRANSLUCENT_LIST (1 << 9)
#define ISTNRM__END_OF_TRANSFERRING_OPAQUE_MODIFIER_VOLUME_LIST (1 << 8)
#define ISTNRM__END_OF_TRANSFERRING_OPAQUE_LIST (1 << 7)
#define ISTNRM__END_OF_TRANSFERRING_YUV (1 << 6)
#define ISTNRM__H_BLANK_IN_INTERRUPT (1 << 5)
#define ISTNRM__V_BLANK_OUT_INTERRUPT (1 << 4)
#define ISTNRM__V_BLANK_IN_INTERRUPT (1 << 3)
#define ISTNRM__END_OF_RENDER_TSP (1 << 2)
#define ISTNRM__END_OF_RENDER_ISP (1 << 1)
#define ISTNRM__END_OF_RENDER_VIDEO (1 << 0)

#define ISTERR__SH4__IF_ACCESS_INHIBITED_AREA (1 << 31)
#define ISTERR__DDT__IF_SORT_DMA_COMMAND_ERROR (1 << 28)
#define ISTERR__G2__TIME_OUT_IN_CPU_ACCESS (1 << 27)
#define ISTERR__G2__DEV_DMA_TIME_OUT (1 << 26)
#define ISTERR__G2__EXT_DMA2_TIME_OUT (1 << 25)
#define ISTERR__G2__EXT_DMA1_TIME_OUT (1 << 24)
#define ISTERR__G2__AICA_DMA_TIME_OUT (1 << 23)
#define ISTERR__G2__DEV_DMA_OVER_RUN (1 << 22)
#define ISTERR__G2__EXT_DMA2_OVER_RUN (1 << 21)
#define ISTERR__G2__EXT_DMA1_OVER_RUN (1 << 20)
#define ISTERR__G2__AICA_DMA_OVER_RUN (1 << 19)
#define ISTERR__G2__DEV_DMA_ILLEGAL_ADDRESS_SET (1 << 18)
#define ISTERR__G2__EXT_DMA2_ILLEGAL_ADDRESS_SET (1 << 17)
#define ISTERR__G2__EXT_DMA1_ILLEGAL_ADDRESS_SET (1 << 16)
#define ISTERR__G2__AICA_DMA_ILLEGAL_ADDRESS_SET (1 << 15)
#define ISTERR__G1__ROM_FLASH_ACCESS_AT_GD_DMA (1 << 14)
#define ISTERR__G1__GD_DMA_OVER_RUN (1 << 13)
#define ISTERR__G1__ILLEGAL_ADDRESS_SET (1 << 12)
#define ISTERR__MAPLE__ILLEGAL_COMMAND (1 << 11)
#define ISTERR__MAPLE__WRITE_FIFO_OVER_FLOW (1 << 10)
#define ISTERR__MAPLE__DMA_OVER_RUN (1 << 9)
#define ISTERR__MAPLE__ILLEGAL_ADDRESS_SET (1 << 8)
#define ISTERR__PVRIF__DMA_OVER_RUN (1 << 7)
#define ISTERR__PVRIF__ILLEGAL_ADDRESS_SET (1 << 6)
#define ISTERR__TA__FIFO_OVERFLOW (1 << 5)
#define ISTERR__TA__ILLEGAL_PARAMETER (1 << 4)
#define ISTERR__TA__OBJECT_LIST_POINTER_OVERFLOW (1 << 3)
#define ISTERR__TA__ISP_TSP_PARAMETER_OVERFLOW (1 << 2)
#define ISTERR__RENDER__HAZARD_PROCESSING_OF_STRIP_BUFFER (1 << 1)
#define ISTERR__RENDER__ISP_OUT_OF_CACHE (1 << 0)
