triangle_ta: reorder SH4 store queue comment
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@ -255,6 +255,37 @@ void transfer_isp_tsp_background_parameter(uint32_t isp_tsp_parameter_start)
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#define ISP_BACKGND_T__TAG_ADDRESS(n) (((n) & 0x1fffff) << 3)
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#define ISP_BACKGND_T__TAG_ADDRESS(n) (((n) & 0x1fffff) << 3)
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#define ISP_BACKGND_T__TAG_OFFSET(n) (((n) & 0x7) << 0)
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#define ISP_BACKGND_T__TAG_OFFSET(n) (((n) & 0x7) << 0)
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/******************************************************************************
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SH4 store queue
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******************************************************************************/
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/*
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The TA polygon converter FIFO requires 32-byte bus access. Attempts to access
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the TA with smaller bus accesses will result in incorrect TA operation. The
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Dreamcast has three mechanisms that can generate 32-byte writes:
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- SH4 store queue (commonly used)
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- Holly CH2-DMA (commonly used)
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- meticulous and clever use of SH4 cache writeback (esoteric forbidden technique)
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Of these, the mechanism that requires the least code is the SH4 store queue,
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so this demo will also use the SH4 store queue for that reason.
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The SH4 store queue is described in sh7091pm_e.pdf printed page 61-64 and
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79-81.
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*/
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// sh7091pm_e.pdf:
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// > Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a
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// > burst transfer from the SQs to external memory.
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#define pref(address) \
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{ asm volatile ("pref @%0" : : "r" (address) : "memory"); }
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volatile uint32_t * SH7091__CCN__QACR0 = (volatile uint32_t *)(0xff000000 + 0x38);
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volatile uint32_t * SH7091__CCN__QACR1 = (volatile uint32_t *)(0xff000000 + 0x3c);
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/******************************************************************************
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/******************************************************************************
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TA Parameters
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TA Parameters
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******************************************************************************/
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******************************************************************************/
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@ -330,17 +361,6 @@ typedef struct ta_vertex_parameter__polygon_type_0 {
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} ta_vertex_parameter__polygon_type_0;
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} ta_vertex_parameter__polygon_type_0;
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static_assert((sizeof (struct ta_vertex_parameter__polygon_type_0)) == 32);
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static_assert((sizeof (struct ta_vertex_parameter__polygon_type_0)) == 32);
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/*
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sh7091pm_e.pdf:
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> Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from
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> the SQs to external memory.
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*/
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#define pref(address) \
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{ asm volatile ("pref @%0" : : "r" (address) : "memory"); }
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volatile uint32_t * SH7091__CCN__QACR0 = (volatile uint32_t *)(0xff000000 + 0x38);
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volatile uint32_t * SH7091__CCN__QACR1 = (volatile uint32_t *)(0xff000000 + 0x3c);
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__END_OF_LIST (0 << 29)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__END_OF_LIST (0 << 29)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__POLYGON_OR_MODIFIER_VOLUME (4 << 29)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__POLYGON_OR_MODIFIER_VOLUME (4 << 29)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__VERTEX_PARAMETER (7 << 29)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__PARA_TYPE__VERTEX_PARAMETER (7 << 29)
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@ -348,6 +368,7 @@ volatile uint32_t * SH7091__CCN__QACR1 = (volatile uint32_t *)(0xff000000 + 0x3c
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__LIST_TYPE__OPAQUE (0 << 24)
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#define PARAMETER_CONTROL_WORD__PARA_CONTROL__LIST_TYPE__OPAQUE (0 << 24)
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#define PARAMETER_CONTROL_WORD__OBJ_CONTROL__COL_TYPE__PACKED_COLOR (0 << 4)
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#define PARAMETER_CONTROL_WORD__OBJ_CONTROL__COL_TYPE__PACKED_COLOR (0 << 4)
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#define PARAMETER_CONTROL_WORD__OBJ_CONTROL__GOURAUD (1 << 1)
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#define PARAMETER_CONTROL_WORD__OBJ_CONTROL__GOURAUD (1 << 1)
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void transfer_ta_triangle()
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void transfer_ta_triangle()
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{
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{
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// set the store queue destination address to the TA Polygon Converter FIFO
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// set the store queue destination address to the TA Polygon Converter FIFO
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@ -459,28 +480,6 @@ void transfer_ta_triangle()
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store_queue_ix += (sizeof (ta_global_parameter__end_of_list));
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store_queue_ix += (sizeof (ta_global_parameter__end_of_list));
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}
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}
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/******************************************************************************
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SH4 store queue
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******************************************************************************/
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/*
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The TA polygon converter FIFO requires 32-byte bus access. Attempts to access
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the TA with smaller bus accesses will result in incorrect TA operation. The
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Dreamcast has three mechanisms that can generate 32-byte writes:
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- SH4 store queue (commonly used)
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- Holly CH2-DMA (commonly used)
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- meticulous and clever use of SH4 cache writeback (esoteric forbidden technique)
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Of these, the mechanism that requires the least code is the SH4 store queue,
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so this demo will also use the SH4 store queue for that reason.
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The SH4 store queue is described in sh7091pm_e.pdf printed page 61-64 and
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79-81.
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*/
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/******************************************************************************
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/******************************************************************************
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Holly register definitions
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Holly register definitions
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******************************************************************************/
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******************************************************************************/
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