186 lines
4.3 KiB
NASM
186 lines
4.3 KiB
NASM
; -*-asm-*-
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changecom(`@')
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;; VIA: 8000
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define(PORTB, h8000)
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define(PORTA, h8001)
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define(DDRB, h8002)
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define(DDRA, h8003)
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define(`L_CGRAM', `0b01000000')
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define(`L_DDRAM', `0b10000000')
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define(`L_E', `0b001')
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define(`L_RS', `0b010')
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define(`L_RW', `0b100')
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define(`hh', `eval($1, 16)')
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define(`bh', `eval(0b$1, 16)')
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;; reset stack
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reset: LDX # ff
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TXS i
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;; Set pins 0-2 on Port A to Output
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LDA # bh(00000111)
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STA a DDRA
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;; Function Set:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 0 1 B L F x x
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;; (Bits 8/4, Lines 2/1, Font 5x11/5x8)
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LDA # bh(00111000)
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JSR a :lcd-w-rs0
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;; Display ON/OFF:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 0 0 0 0 D C B
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;; (Display, Cursor, Blink)
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LDA # bh(00001110)
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JSR a :lcd-w-rs0
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;; Clear Display:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 0 0 0 0 0 0 1
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LDA # bh(00000001)
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JSR a :lcd-w-rs0
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;; Entry Mode Set:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 0 0 0 0 1 I/D S
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;; (Increment/Decrement, Shift)
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LDA # bh(00000110)
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JSR a :lcd-w-rs0
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;; Set DDRAM Address:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 1 A6 A5 A4 A3 A2 A1 A0
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LDA # hh(L_DDRAM|0)
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JSR a :lcd-w-rs0
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;; Write Data:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; D D D D D D D D
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LDA # 0
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JSR a :lcd-w-rs1
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;; Write Data:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; D D D D D D D D
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LDA # 1
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JSR a :lcd-w-rs1
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;; Set CGRAM Address:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 1 AC5 AC4 AC3 AC2 AC1 AC0
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LDA # hh(L_CGRAM|0)
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JSR a :lcd-w-rs0
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;; data is at e000
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LDA # 00
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STA zp 00
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LDA # e0
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STA zp 01
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;; 16
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LDX # 16
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LDY # 0
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loop: LDA (zp),y 00
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;; Write Data to CGRAM
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; D D D D D D D D
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;; RS:1 RW:0
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STA a PORTB
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JSR a :lcd-w-rs1
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INY i
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DEX i
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BNE r :loop
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;; Display ON/OFF:
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 0 0 0 0 D C B
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;; (Display, Cursor, Blink)
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LDA # bh(00001100)
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JSR a :lcd-w-rs0
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;; Set CGRAM Address
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 1 AC5 AC4 AC3 AC2 AC1 AC0
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loop2: LDA # hh(L_CGRAM|9)
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JSR a :lcd-w-rs0
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;; Write Data to CGRAM
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; D D D D D D D D
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LDA # bh(00110)
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JSR a :lcd-w-rs1
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;; Set CGRAM Address
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; 0 1 AC5 AC4 AC3 AC2 AC1 AC0
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LDA # hh(L_CGRAM|9)
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JSR a :lcd-w-rs0
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;; Write Data to CGRAM
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;; D7 D6 D5 D4 D3 D2 D1 D0
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;; D D D D D D D D
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LDA # bh(00000)
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JSR a :lcd-w-rs1
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JMP a :loop2
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stop: JMP a :stop
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;; write "instruction"
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lcd-w-rs0: JSR a :lcd-wait
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STA a PORTB
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LDA # 0
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STA a PORTA
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LDA # hh(L_E)
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STA a PORTA
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LDA # 0
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STA a PORTA
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RTS s
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;; write "data" to lcd
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lcd-w-rs1: JSR a :lcd-wait
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STA a PORTB
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LDA # hh(L_RS)
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STA a PORTA
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LDA # hh(L_RS|L_E)
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STA a PORTA
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LDA # hh(L_RS)
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STA a PORTA
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RTS s
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;; wait BF
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lcd-wait: PHA s
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LDA # bh(00000000) ;; Set pins 0-7 on Port B to Input
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STA a DDRB
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_lcd_wait: LDA # hh(L_RW)
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STA a PORTA
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LDA # hh(L_E|L_RW)
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STA a PORTA
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LDA a PORTB
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AND # bh(10000000)
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BNE r :_lcd_wait
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LDA # hh(L_RW)
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STA a PORTA
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LDA # bh(11111111) ;; Set pins 0-7 on Port B to Output
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STA a DDRB
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PLA s
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RTS s
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