include(`common.m4')

define(KBD_STATE, 0x40) ;;; 0x40 - 0x80

        BRA r :reset ; RESB
        NOP i        ; IRQ

reset:  LDX # ff
        TXS i

        JSR a :lcd_init

        ;; LDA # 61
        ;; JSR a :lcd_w_rs1

        LDA # %11111111
        STA a VIA1_PORTA

        LDA # %00000000
        STA a VIA1_DDRB

        LDA # %11111111
        STA a VIA1_DDRA


        LDX # 80
        LDA # f
_state: STA zp,x hh(KBD_STATE)
        DEX i
        BNE r :_state


forever:        LDX # 7         ; state
        LDA # %01111111
        STA zp 0

loop0:  LDA zp 0
        STA a VIA1_PORTA

                LDY # 4         ; bit
                LDA a VIA1_PORTB
loop1:          ROR A
                PHP s
                PHA s
        ;; (X * 8 + Y) * 2
                TYA i
                STA zp 1
                TXA i
                ASL A
                ASL A
                ASL A
                CLC i
                ADC zp 1
                ASL A
        ;;
                STX zp 1
                TAX i
                PLP s
                BCS r :_kbd_up

                LSR A                ;
                JSR a :lcd_w_rs1     ;
                BPL r :_loop1_resume ;

_kbd_down:      DEC zp,x hh(KBD_STATE)
                BPL r :_loop1_resume
                BNE r :_key_not_yet_down

        ;; if (KBD_STATE[X][0] == 0) {
                LSR A
                TAX i
                LDA a,x :_bin_keymap_start
                JSR a :lcd_w_rs1
        ;; }


_key_not_yet_down:      LDA # ff
                        STA zp,x hh(KBD_STATE)
                        LDA # f
                        STA zp,x hh(KBD_STATE + 1)

                BRA r :_loop1_resume
;;; Y is the offset of the current key
_kbd_up:        DEC zp,x hh(KBD_STATE + 1)
                BPL r :_loop1_resume

                        LDA # ff
                        STA zp,x hh(KBD_STATE + 1)
                        LDA # f
                        STA zp,x hh(KBD_STATE)

_loop1_resume:  PLA s
                LDX zp 1
                DEY i
                BPL r :loop1

        SEC i
        ROR zp 0
        DEX i
        BPL r :loop0

        BRA r :forever


                        ;; LDA # %00000001
                        ;; JSR a :lcd_w_rs0

                        ;; TXA i
                        ;; CLC i
                        ;; ADC # 30
                        ;; STA a VIA1_PORTB
                        ;; JSR a :lcd_w_rs1

                        ;; LDA # 20
                        ;; JSR a :lcd_w_rs1

                        ;; TYA i
                        ;; CLC i
                        ;; ADC # 30
                        ;; STA a VIA1_PORTB
                        ;; JSR a :lcd_w_rs1