changecom(`@')dnl
dnl
define(VIA0_PORTB, 8000)dnl
define(VIA0_PORTA, 8001)dnl
define(VIA0_DDRB, 8002)dnl
define(VIA0_DDRA, 8003)dnl
define(VIA0_T1CL, 8004)dnl
define(VIA0_T1CH, 8005)dnl
define(VIA0_T1LL, 8006)dnl
define(VIA0_T1LH, 8007)dnl
define(VIA0_T2CL, 8008)dnl
define(VIA0_T2CH, 8009)dnl
define(VIA0_SR, 800a)dnl
define(VIA0_ACR, 800b)dnl
define(VIA0_PCR, 800c)dnl
define(VIA0_IFR, 800d)dnl
define(VIA0_IER, 800e)dnl
dnl
define(VIA1_PORTB, 8800)dnl
define(VIA1_PORTA, 8801)dnl
define(VIA1_DDRB, 8802)dnl
define(VIA1_DDRA, 8803)dnl
define(VIA1_T1CL, 8804)dnl
define(VIA1_T1CH, 8805)dnl
define(VIA1_T1LL, 8806)dnl
define(VIA1_T1LH, 8807)dnl
define(VIA1_T2CL, 8808)dnl
define(VIA1_T2CH, 8809)dnl
define(VIA1_SR, 880a)dnl
define(VIA1_ACR, 880b)dnl
define(VIA1_PCR, 880c)dnl
define(VIA1_IFR, 880d)dnl
define(VIA1_IER, 880e)dnl
dnl
define(VIA2_PORTB, 9000)dnl
define(VIA2_PORTA, 9001)dnl
define(VIA2_DDRB, 9002)dnl
define(VIA2_DDRA, 9003)dnl
define(VIA2_T1CL, 9004)dnl
define(VIA2_T1CH, 9005)dnl
define(VIA2_T1LL, 9006)dnl
define(VIA2_T1LH, 9007)dnl
define(VIA2_T2CL, 9008)dnl
define(VIA2_T2CH, 9009)dnl
define(VIA2_SR, 900a)dnl
define(VIA2_ACR, 900b)dnl
define(VIA2_PCR, 900c)dnl
define(VIA2_IFR, 900d)dnl
define(VIA2_IER, 900e)dnl
dnl ACR
dnl ACR
define(`ACR_SR_DISABLED', `0b00000000')dnl
define(`ACR_SR_IN_T2', `0b00000100')dnl
define(`ACR_SR_IN_PHI2', `0b00001000')dnl
define(`ACR_SR_IN_CB1', `0b00001100')dnl
define(`ACR_SR_OUT_FREE_T2', `0b00010000')dnl
define(`ACR_SR_OUT_T2', `0b00010100')dnl
define(`ACR_SR_OUT_PHI2', `0b00011000')dnl
define(`ACR_SR_OUT_CB1', `0b00011100')dnl
dnl LCD common
define(`L_DDR_MASK', `0b11111111')dnl
dnl character LCD
define(`C_CGRAM', `0b01000000')dnl
define(`C_DDRAM', `0b10000000')dnl
dnl
define(`C_E', `0b00000001')dnl
define(`C_RS', `0b00010000')dnl
define(`C_RW', `0b00100000')dnl
dnl
define(`hh', `eval($1, 16)')dnl
dnl graphic LCD
define(`G_E', `0b00000010')dnl
define(`G_C1', `0b00000100')dnl
define(`G_C2', `0b00001000')dnl
define(`G_RS', `0b00010000')dnl
define(`G_RW', `0b00100000')dnl
dnl MAX3100
define(`M_DDR_MASK', `0b01110000')dnl
define(`M_DOUT', `0b10000000')dnl input
define(`M_DIN', `0b01000000')dnl output
define(`M_SCLK', `0b00100000')dnl output
define(`M_CS', `0b00010000')dnl output
dnl MAX3100 CFG bits
define(`M_CFGH', `0b11000000')dnl
define(`M_CFGH_FENB', `0b00100000')dnl 0=enable FIFO
define(`M_CFGH_SHDN', `0b00010000')dnl 1=shutdown
define(`M_CFGH_TMB', `0b00001000')dnl  1=enable transmit done interrupt
define(`M_CFGH_RMB', `0b00000100')dnl  1=enable data received interrupt
define(`M_CFGH_PMB', `0b00000010')dnl  1=enable parity interrupt
define(`M_CFGH_RAMB', `0b00000001')dnl 1=enable framing error interrupt
define(`M_CFGL_IR', `0b10000000')dnl   1=enable IrDA timing mode
define(`M_CFGL_ST', `0b01000000')dnl   1=two stop bits
define(`M_CFGL_PE', `0b00100000')dnl   1=parity enabled
define(`M_CFGL_L', `0b00010000')dnl    1=7-bits; 0=8-bits
define(`M_CFGL_BAUD_230400', `0b00000000')dnl
define(`M_CFGL_BAUD_115200', `0b00000001')dnl
define(`M_CFGL_BAUD_57600', `0b00000010')dnl
define(`M_CFGL_BAUD_38400', `0b00001001')dnl
define(`M_CFGL_BAUD_19200', `0b00001010')dnl
define(`M_CFGL_BAUD_9600', `0b00001011')dnl
define(`M_CFGL_BAUD_600', `0b00001111')dnl
dnl MAX3100 data bits
define(`M_R_DATA', `0b00000000')dnl
define(`M_W_DATAH', `0b10000000')dnl
define(`M_W_DATAH_TE', `0b00000100')dnl  1=inhibit TX
define(`M_W_DATAH_RTS', `0b00000010')dnl 1=drive RTS low; 0=drive RTS high
define(`M_W_DATAH_PT', `0b00000001')dnl  1=parity1; 0=parity0
dnl bit7 high "data has been received"
dnl bit6 high "transmit buffer empty"