6502-sim/instruction.c

#include "instruction.h"
#include "opcodes.h"

const struct instruction decode_ins[256] = {
  {BRK, S},
  {ORA, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {TSB, ZP},
  {ORA, ZP},
  {ASL, ZP},
  {RMB0, ZP},
  {PHP, S},
  {ORA, IMM},
  {ASL, ACC},
  {O_INVALID, M_INVALID},
  {TSB, A},
  {ORA, A},
  {ASL, A},
  {BBR0, R},

  {BPL, R},
  {ORA, ZPIY},
  {ORA, ZPI},
  {O_INVALID, M_INVALID},
  {TRB, ZP},
  {ORA, ZPX},
  {ASL, ZPX},
  {RMB1, ZP},
  {CLC, I},
  {ORA, AIY},
  {INC, ACC},
  {O_INVALID, M_INVALID},
  {TRB, A},
  {ORA, AIX},
  {ASL, AIX},
  {BBR1, R},

  {JSR, A},
  {AND, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {BIT, ZP},
  {AND, ZP},
  {ROL, ZP},
  {RMB2, ZP},
  {PLP, S},
  {AND, IMM},
  {ROL, ACC},
  {O_INVALID, M_INVALID},
  {BIT, A},
  {AND, A},
  {ROL, A},
  {BBR2, R},

  {BMI, R},
  {AND, ZPIY},
  {AND, ZPI},
  {O_INVALID, M_INVALID},
  {BIT, ZPX},
  {AND, ZPX},
  {ROL, ZPX},
  {RMB3, ZP},
  {SEC, I},
  {AND, AIY},
  {DEC, ACC},
  {O_INVALID, M_INVALID},
  {BIT, AIX},
  {AND, AIX},
  {ROL, AIX},
  {BBR3, R},

  {RTI, S},
  {EOR, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {EOR, ZP},
  {LSR, ZP},
  {RMB4, ZP},
  {PHA, S},
  {EOR, IMM},
  {LSR, ACC},
  {O_INVALID, M_INVALID},
  {JMP, A},
  {EOR, A},
  {LSR, A},
  {BBR4, R},

  {BVC, R},
  {EOR, ZPIY},
  {EOR, ZPI},
  {EOR, ZPX},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {LSR, ZPX},
  {RMB5, ZP},
  {CLI, I},
  {EOR, AIY},
  {PHY, S},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {EOR, AIX},
  {LSR, AIX},
  {BBR5, R},

  {RTS, S},
  {ADC, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {STZ, ZP},
  {ADC, ZP},
  {ROR, ZP},
  {RMB6, ZP},
  {PLA, S},
  {ADC, IMM},
  {ROR, ACC},
  {O_INVALID, M_INVALID},
  {JMP, AI},
  {ADC, A},
  {ROR, A},
  {BBR6, R},

  {BVS, R},
  {ADC, ZPIY},
  {ADC, ZPI},
  {O_INVALID, M_INVALID},
  {STZ, ZPX},
  {ADC, ZPX},
  {ROR, ZPX},
  {RMB7, ZP},
  {SEI, I},
  {ADC, AIY},
  {PLY, S},
  {O_INVALID, M_INVALID},
  {JMP, AII},
  {ADC, AIX},
  {ROR, AIX},
  {BBR7, R},

  {BRA, R},
  {STA, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {STY, ZP},
  {STA, ZP},
  {STX, ZP},
  {SMB0, ZP},
  {DEY, I},
  {BIT, IMM},
  {TXA, I},
  {O_INVALID, M_INVALID},
  {STY, A},
  {STA, A},
  {STX, A},
  {BBS0, R},

  {BCC, R},
  {STA, ZPIY},
  {STA, ZPI},
  {O_INVALID, M_INVALID},
  {STY, ZPX},
  {STA, ZPX},
  {STX, ZPY},
  {SMB1, ZP},
  {TYA, I},
  {STA, AIY},
  {TXS, I},
  {O_INVALID, M_INVALID},
  {STZ, A},
  {STA, AIX},
  {STZ, AIX},
  {BBS1, R},

  {LDY, IMM},
  {LDA, ZPII},
  {LDX, IMM},
  {O_INVALID, M_INVALID},
  {LDY, ZP},
  {LDA, ZP},
  {LDX, ZP},
  {SMB2, ZP},
  {TAY, I},
  {LDA, IMM},
  {TAX, I},
  {O_INVALID, M_INVALID},
  {LDY, A},
  {LDA, A},
  {LDX, A},
  {BBS2, R},

  {BCS, R},
  {LDA, ZPIY},
  {LDA, ZPI},
  {O_INVALID, M_INVALID},
  {LDY, ZPX},
  {LDA, ZPX},
  {LDX, ZPY},
  {SMB3, ZP},
  {CLV, I},
  {LDA, AIY},
  {TSX, I},
  {O_INVALID, M_INVALID},
  {LDY, AIX},
  {LDA, AIX},
  {LDX, AIY},
  {BBS3, R},

  {CPY, IMM},
  {CMP, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {CPY, ZP},
  {CMP, ZP},
  {DEC, ZP},
  {SMB4, ZP},
  {INY, I},
  {CMP, IMM},
  {DEX, I},
  {WAI, I},
  {CPY, A},
  {CMP, A},
  {DEC, A},
  {BBS4, R},

  {BNE, R},
  {CMP, ZPIY},
  {CMP, ZPI},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {CMP, ZPX},
  {DEC, ZPX},
  {SMB5, ZP},
  {CLD, I},
  {CMP, AIY},
  {PHX, S},
  {STP, I},
  {O_INVALID, M_INVALID},
  {CMP, AIX},
  {DEC, AIX},
  {BBS5, R},

  {CPX, IMM},
  {SBC, ZPII},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {CPX, ZP},
  {SBC, ZP},
  {INC, ZP},
  {SMB6, ZP},
  {INX, I},
  {SBC, IMM},
  {NOP, I},
  {O_INVALID, M_INVALID},
  {CPX, A},
  {SBC, A},
  {INC, A},
  {BBS6, R},

  {BEQ, R},
  {SBC, ZPIY},
  {SBC, ZPI},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {SBC, ZPX},
  {INC, ZPX},
  {SMB7, ZP},
  {SED, I},
  {SBC, AIY},
  {PLX, S},
  {O_INVALID, M_INVALID},
  {O_INVALID, M_INVALID},
  {SBC, AIX},
  {INC, AIX},
  {BBS7, R},
};