#include <array>
#include <cstdint>
#include <map>
#include <tuple>

#include "codec.hh"
#include "isa.hh"

namespace codec {
  const std::map<std::tuple<isa::op, isa::mode>, uint8_t>& encode() {
    static const std::map<std::tuple<isa::op, isa::mode>, uint8_t> _ = {
      {{isa::op::BRK, isa::mode::S}, 0},
      {{isa::op::ORA, isa::mode::ZPX}, 1},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 2},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 3},
      {{isa::op::TSB, isa::mode::ZP}, 4},
      {{isa::op::ORA, isa::mode::ZP}, 5},
      {{isa::op::ASL, isa::mode::ZP}, 6},
      {{isa::op::RMB0, isa::mode::ZP}, 7},
      {{isa::op::PHP, isa::mode::S}, 8},
      {{isa::op::ORA, isa::mode::IMM}, 9},
      {{isa::op::ASL, isa::mode::A}, 10},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 11},
      {{isa::op::TSB, isa::mode::A}, 12},
      {{isa::op::ORA, isa::mode::A}, 13},
      {{isa::op::ASL, isa::mode::A}, 14},
      {{isa::op::BBR0, isa::mode::R}, 15},

      {{isa::op::BPL, isa::mode::R}, 16},
      {{isa::op::ORA, isa::mode::ZPIY}, 17},
      {{isa::op::ORA, isa::mode::ZPI}, 18},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 19},
      {{isa::op::TRB, isa::mode::ZP}, 20},
      {{isa::op::ORA, isa::mode::ZPX}, 21},
      {{isa::op::ASL, isa::mode::ZPX}, 22},
      {{isa::op::RMB1, isa::mode::ZP}, 23},
      {{isa::op::CLC, isa::mode::I}, 24},
      {{isa::op::ORA, isa::mode::AIY}, 25},
      {{isa::op::INC, isa::mode::A}, 26},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 27},
      {{isa::op::TRB, isa::mode::A}, 28},
      {{isa::op::ORA, isa::mode::AIX}, 29},
      {{isa::op::ASL, isa::mode::AIX}, 30},
      {{isa::op::BBR1, isa::mode::R}, 31},

      {{isa::op::JSR, isa::mode::A}, 32},
      {{isa::op::AND, isa::mode::ZPII}, 33},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 34},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 35},
      {{isa::op::BIT, isa::mode::ZP}, 36},
      {{isa::op::AND, isa::mode::ZP}, 37},
      {{isa::op::ROL, isa::mode::ZP}, 38},
      {{isa::op::RMB2, isa::mode::ZP}, 39},
      {{isa::op::PLP, isa::mode::S}, 40},
      {{isa::op::AND, isa::mode::IMM}, 41},
      {{isa::op::ROL, isa::mode::A}, 42},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 43},
      {{isa::op::BIT, isa::mode::A}, 44},
      {{isa::op::AND, isa::mode::A}, 45},
      {{isa::op::ROL, isa::mode::A}, 46},
      {{isa::op::BBR2, isa::mode::R}, 47},

      {{isa::op::BMI, isa::mode::R}, 48},
      {{isa::op::AND, isa::mode::ZPIY}, 49},
      {{isa::op::AND, isa::mode::ZPI}, 50},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 51},
      {{isa::op::BIT, isa::mode::ZPX}, 52},
      {{isa::op::AND, isa::mode::ZPX}, 53},
      {{isa::op::ROL, isa::mode::ZPX}, 54},
      {{isa::op::RMB3, isa::mode::ZP}, 55},
      {{isa::op::SEC, isa::mode::I}, 56},
      {{isa::op::AND, isa::mode::AIY}, 57},
      {{isa::op::DEC, isa::mode::A}, 58},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 59},
      {{isa::op::BIT, isa::mode::AIX}, 60},
      {{isa::op::AND, isa::mode::AIX}, 61},
      {{isa::op::ROL, isa::mode::AIX}, 62},
      {{isa::op::BBR3, isa::mode::R}, 63},

      {{isa::op::RTI, isa::mode::S}, 64},
      {{isa::op::EOR, isa::mode::ZPII}, 65},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 66},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 67},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 68},
      {{isa::op::EOR, isa::mode::ZP}, 69},
      {{isa::op::LSR, isa::mode::ZP}, 70},
      {{isa::op::RMB4, isa::mode::ZP}, 71},
      {{isa::op::PHA, isa::mode::S}, 72},
      {{isa::op::EOR, isa::mode::IMM}, 73},
      {{isa::op::LSR, isa::mode::A}, 74},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 75},
      {{isa::op::JMP, isa::mode::A}, 76},
      {{isa::op::EOR, isa::mode::A}, 77},
      {{isa::op::LSR, isa::mode::A}, 78},
      {{isa::op::BBR4, isa::mode::R}, 79},

      {{isa::op::BVC, isa::mode::R}, 80},
      {{isa::op::EOR, isa::mode::ZPIY}, 81},
      {{isa::op::EOR, isa::mode::ZPI}, 82},
      {{isa::op::EOR, isa::mode::ZPX}, 83},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 84},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 85},
      {{isa::op::LSR, isa::mode::ZPX}, 86},
      {{isa::op::RMB5, isa::mode::ZP}, 87},
      {{isa::op::CLI, isa::mode::I}, 88},
      {{isa::op::EOR, isa::mode::AIY}, 89},
      {{isa::op::PHY, isa::mode::S}, 90},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 91},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 92},
      {{isa::op::EOR, isa::mode::AIX}, 93},
      {{isa::op::LSR, isa::mode::AIX}, 94},
      {{isa::op::BBR5, isa::mode::R}, 95},

      {{isa::op::RTS, isa::mode::S}, 96},
      {{isa::op::ADC, isa::mode::ZPII}, 97},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 98},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 99},
      {{isa::op::STZ, isa::mode::ZP}, 100},
      {{isa::op::ADC, isa::mode::ZP}, 101},
      {{isa::op::ROR, isa::mode::ZP}, 102},
      {{isa::op::RMB6, isa::mode::ZP}, 103},
      {{isa::op::PLA, isa::mode::S}, 104},
      {{isa::op::ADC, isa::mode::IMM}, 105},
      {{isa::op::ROR, isa::mode::A}, 106},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 107},
      {{isa::op::JMP, isa::mode::AI}, 108},
      {{isa::op::ADC, isa::mode::A}, 109},
      {{isa::op::ROR, isa::mode::A}, 110},
      {{isa::op::BBR6, isa::mode::R}, 111},

      {{isa::op::BVS, isa::mode::R}, 112},
      {{isa::op::ADC, isa::mode::ZPIY}, 113},
      {{isa::op::ADC, isa::mode::ZPI}, 114},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 115},
      {{isa::op::STZ, isa::mode::ZPX}, 116},
      {{isa::op::ADC, isa::mode::ZPX}, 117},
      {{isa::op::ROR, isa::mode::ZPX}, 118},
      {{isa::op::RMB7, isa::mode::ZP}, 119},
      {{isa::op::SEI, isa::mode::I}, 120},
      {{isa::op::ADC, isa::mode::AIY}, 121},
      {{isa::op::PLY, isa::mode::S}, 122},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 123},
      {{isa::op::JMP, isa::mode::AII}, 124},
      {{isa::op::ADC, isa::mode::AIX}, 125},
      {{isa::op::ROR, isa::mode::AIX}, 126},
      {{isa::op::BBR7, isa::mode::R}, 127},

      {{isa::op::BRA, isa::mode::R}, 128},
      {{isa::op::STA, isa::mode::ZPII}, 129},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 130},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 131},
      {{isa::op::STY, isa::mode::ZP}, 132},
      {{isa::op::STA, isa::mode::ZP}, 133},
      {{isa::op::STX, isa::mode::ZP}, 134},
      {{isa::op::SMB0, isa::mode::ZP}, 135},
      {{isa::op::DEY, isa::mode::I}, 136},
      {{isa::op::BIT, isa::mode::IMM}, 137},
      {{isa::op::TXA, isa::mode::I}, 138},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 139},
      {{isa::op::STY, isa::mode::A}, 140},
      {{isa::op::STA, isa::mode::A}, 141},
      {{isa::op::STX, isa::mode::A}, 142},
      {{isa::op::BBS0, isa::mode::R}, 143},

      {{isa::op::BCC, isa::mode::R}, 144},
      {{isa::op::STA, isa::mode::ZPIY}, 145},
      {{isa::op::STA, isa::mode::ZPI}, 146},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 147},
      {{isa::op::STY, isa::mode::ZPX}, 148},
      {{isa::op::STA, isa::mode::ZPX}, 149},
      {{isa::op::STX, isa::mode::ZPY}, 150},
      {{isa::op::SMB1, isa::mode::ZP}, 151},
      {{isa::op::TYA, isa::mode::I}, 152},
      {{isa::op::STA, isa::mode::AIY}, 153},
      {{isa::op::TXS, isa::mode::I}, 154},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 155},
      {{isa::op::STZ, isa::mode::A}, 156},
      {{isa::op::STA, isa::mode::AIX}, 157},
      {{isa::op::STZ, isa::mode::AIX}, 158},
      {{isa::op::BBS1, isa::mode::R}, 159},

      {{isa::op::LDY, isa::mode::IMM}, 160},
      {{isa::op::LDA, isa::mode::ZPII}, 161},
      {{isa::op::LDX, isa::mode::IMM}, 162},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 163},
      {{isa::op::LDY, isa::mode::ZP}, 164},
      {{isa::op::LDA, isa::mode::ZP}, 165},
      {{isa::op::LDX, isa::mode::ZP}, 166},
      {{isa::op::SMB2, isa::mode::ZP}, 167},
      {{isa::op::TAY, isa::mode::I}, 168},
      {{isa::op::LDA, isa::mode::IMM}, 169},
      {{isa::op::TAX, isa::mode::I}, 170},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 171},
      {{isa::op::LDY, isa::mode::A}, 172},
      {{isa::op::LDA, isa::mode::A}, 173},
      {{isa::op::LDX, isa::mode::A}, 174},
      {{isa::op::BBS2, isa::mode::R}, 175},

      {{isa::op::BCS, isa::mode::R}, 176},
      {{isa::op::LDA, isa::mode::ZPIY}, 177},
      {{isa::op::LDA, isa::mode::ZPI}, 178},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 179},
      {{isa::op::LDY, isa::mode::ZPX}, 180},
      {{isa::op::LDA, isa::mode::ZPX}, 181},
      {{isa::op::LDX, isa::mode::ZPY}, 182},
      {{isa::op::SMB3, isa::mode::ZP}, 183},
      {{isa::op::CLV, isa::mode::I}, 184},
      {{isa::op::LDA, isa::mode::AIY}, 185},
      {{isa::op::TSX, isa::mode::I}, 186},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 187},
      {{isa::op::LDY, isa::mode::AIX}, 188},
      {{isa::op::LDA, isa::mode::AIX}, 189},
      {{isa::op::LDX, isa::mode::AIY}, 190},
      {{isa::op::BBS3, isa::mode::R}, 191},

      {{isa::op::CPY, isa::mode::IMM}, 192},
      {{isa::op::CMP, isa::mode::ZPII}, 193},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 194},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 195},
      {{isa::op::CPY, isa::mode::ZP}, 196},
      {{isa::op::CMP, isa::mode::ZP}, 197},
      {{isa::op::DEC, isa::mode::ZP}, 198},
      {{isa::op::SMB4, isa::mode::ZP}, 199},
      {{isa::op::INY, isa::mode::I}, 200},
      {{isa::op::CMP, isa::mode::IMM}, 201},
      {{isa::op::DEX, isa::mode::I}, 202},
      {{isa::op::WAI, isa::mode::I}, 203},
      {{isa::op::CPY, isa::mode::A}, 204},
      {{isa::op::CMP, isa::mode::A}, 205},
      {{isa::op::DEC, isa::mode::A}, 206},
      {{isa::op::BBS4, isa::mode::R}, 207},

      {{isa::op::BNE, isa::mode::R}, 208},
      {{isa::op::CMP, isa::mode::ZPIY}, 209},
      {{isa::op::CMP, isa::mode::ZPI}, 210},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 211},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 212},
      {{isa::op::CMP, isa::mode::ZPX}, 213},
      {{isa::op::DEC, isa::mode::ZPX}, 214},
      {{isa::op::SMB5, isa::mode::ZP}, 215},
      {{isa::op::CLD, isa::mode::I}, 216},
      {{isa::op::CMP, isa::mode::AIY}, 217},
      {{isa::op::PHX, isa::mode::S}, 218},
      {{isa::op::STP, isa::mode::I}, 219},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 220},
      {{isa::op::CMP, isa::mode::AIX}, 221},
      {{isa::op::DEC, isa::mode::AIX}, 222},
      {{isa::op::BBS5, isa::mode::R}, 223},

      {{isa::op::CPX, isa::mode::IMM}, 224},
      {{isa::op::SBC, isa::mode::ZPII}, 225},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 226},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 227},
      {{isa::op::CPX, isa::mode::ZP}, 228},
      {{isa::op::SBC, isa::mode::ZP}, 229},
      {{isa::op::INC, isa::mode::ZP}, 230},
      {{isa::op::SMB6, isa::mode::ZP}, 231},
      {{isa::op::INX, isa::mode::I}, 232},
      {{isa::op::SBC, isa::mode::IMM}, 233},
      {{isa::op::NOP, isa::mode::I}, 234},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 235},
      {{isa::op::CPX, isa::mode::A}, 236},
      {{isa::op::SBC, isa::mode::A}, 237},
      {{isa::op::INC, isa::mode::A}, 238},
      {{isa::op::BBS6, isa::mode::R}, 239},

      {{isa::op::BEQ, isa::mode::R}, 240},
      {{isa::op::SBC, isa::mode::ZPIY}, 241},
      {{isa::op::SBC, isa::mode::ZPI}, 242},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 243},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 244},
      {{isa::op::SBC, isa::mode::ZPX}, 245},
      {{isa::op::INC, isa::mode::ZPX}, 246},
      {{isa::op::SMB7, isa::mode::ZP}, 247},
      {{isa::op::SED, isa::mode::I}, 248},
      {{isa::op::SBC, isa::mode::AIY}, 249},
      {{isa::op::PLX, isa::mode::S}, 250},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 251},
      //{{isa::op::O_INVALID, isa::mode::M_INVALID}, 252},
      {{isa::op::SBC, isa::mode::AIX}, 253},
      {{isa::op::INC, isa::mode::AIX}, 254},
      {{isa::op::BBS7, isa::mode::R}, 255},
    };
    return _;
  }

  const std::map<uint8_t, std::tuple<isa::op, isa::mode>>& decode() {
    static const std::map<uint8_t, std::tuple<isa::op, isa::mode>> _ = {
      {0, {isa::op::BRK, isa::mode::S}},
      {1, {isa::op::ORA, isa::mode::ZPX}},
      //{2, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{3, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {4, {isa::op::TSB, isa::mode::ZP}},
      {5, {isa::op::ORA, isa::mode::ZP}},
      {6, {isa::op::ASL, isa::mode::ZP}},
      {7, {isa::op::RMB0, isa::mode::ZP}},
      {8, {isa::op::PHP, isa::mode::S}},
      {9, {isa::op::ORA, isa::mode::IMM}},
      {10, {isa::op::ASL, isa::mode::A}},
      //{11, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {12, {isa::op::TSB, isa::mode::A}},
      {13, {isa::op::ORA, isa::mode::A}},
      {14, {isa::op::ASL, isa::mode::A}},
      {15, {isa::op::BBR0, isa::mode::R}},

      {16, {isa::op::BPL, isa::mode::R}},
      {17, {isa::op::ORA, isa::mode::ZPIY}},
      {18, {isa::op::ORA, isa::mode::ZPI}},
      //{19, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {20, {isa::op::TRB, isa::mode::ZP}},
      {21, {isa::op::ORA, isa::mode::ZPX}},
      {22, {isa::op::ASL, isa::mode::ZPX}},
      {23, {isa::op::RMB1, isa::mode::ZP}},
      {24, {isa::op::CLC, isa::mode::I}},
      {25, {isa::op::ORA, isa::mode::AIY}},
      {26, {isa::op::INC, isa::mode::A}},
      //{27, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {28, {isa::op::TRB, isa::mode::A}},
      {29, {isa::op::ORA, isa::mode::AIX}},
      {30, {isa::op::ASL, isa::mode::AIX}},
      {31, {isa::op::BBR1, isa::mode::R}},

      {32, {isa::op::JSR, isa::mode::A}},
      {33, {isa::op::AND, isa::mode::ZPII}},
      //{34, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{35, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {36, {isa::op::BIT, isa::mode::ZP}},
      {37, {isa::op::AND, isa::mode::ZP}},
      {38, {isa::op::ROL, isa::mode::ZP}},
      {39, {isa::op::RMB2, isa::mode::ZP}},
      {40, {isa::op::PLP, isa::mode::S}},
      {41, {isa::op::AND, isa::mode::IMM}},
      {42, {isa::op::ROL, isa::mode::A}},
      //{43, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {44, {isa::op::BIT, isa::mode::A}},
      {45, {isa::op::AND, isa::mode::A}},
      {46, {isa::op::ROL, isa::mode::A}},
      {47, {isa::op::BBR2, isa::mode::R}},

      {48, {isa::op::BMI, isa::mode::R}},
      {49, {isa::op::AND, isa::mode::ZPIY}},
      {50, {isa::op::AND, isa::mode::ZPI}},
      //{51, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {52, {isa::op::BIT, isa::mode::ZPX}},
      {53, {isa::op::AND, isa::mode::ZPX}},
      {54, {isa::op::ROL, isa::mode::ZPX}},
      {55, {isa::op::RMB3, isa::mode::ZP}},
      {56, {isa::op::SEC, isa::mode::I}},
      {57, {isa::op::AND, isa::mode::AIY}},
      {58, {isa::op::DEC, isa::mode::A}},
      //{59, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {60, {isa::op::BIT, isa::mode::AIX}},
      {61, {isa::op::AND, isa::mode::AIX}},
      {62, {isa::op::ROL, isa::mode::AIX}},
      {63, {isa::op::BBR3, isa::mode::R}},

      {64, {isa::op::RTI, isa::mode::S}},
      {65, {isa::op::EOR, isa::mode::ZPII}},
      //{66, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{67, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{68, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {69, {isa::op::EOR, isa::mode::ZP}},
      {70, {isa::op::LSR, isa::mode::ZP}},
      {71, {isa::op::RMB4, isa::mode::ZP}},
      {72, {isa::op::PHA, isa::mode::S}},
      {73, {isa::op::EOR, isa::mode::IMM}},
      {74, {isa::op::LSR, isa::mode::A}},
      //{75, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {76, {isa::op::JMP, isa::mode::A}},
      {77, {isa::op::EOR, isa::mode::A}},
      {78, {isa::op::LSR, isa::mode::A}},
      {79, {isa::op::BBR4, isa::mode::R}},

      {80, {isa::op::BVC, isa::mode::R}},
      {81, {isa::op::EOR, isa::mode::ZPIY}},
      {82, {isa::op::EOR, isa::mode::ZPI}},
      {83, {isa::op::EOR, isa::mode::ZPX}},
      //{84, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{85, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {86, {isa::op::LSR, isa::mode::ZPX}},
      {87, {isa::op::RMB5, isa::mode::ZP}},
      {88, {isa::op::CLI, isa::mode::I}},
      {89, {isa::op::EOR, isa::mode::AIY}},
      {90, {isa::op::PHY, isa::mode::S}},
      //{91, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{92, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {93, {isa::op::EOR, isa::mode::AIX}},
      {94, {isa::op::LSR, isa::mode::AIX}},
      {95, {isa::op::BBR5, isa::mode::R}},

      {96, {isa::op::RTS, isa::mode::S}},
      {97, {isa::op::ADC, isa::mode::ZPII}},
      //{98, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{99, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {100, {isa::op::STZ, isa::mode::ZP}},
      {101, {isa::op::ADC, isa::mode::ZP}},
      {102, {isa::op::ROR, isa::mode::ZP}},
      {103, {isa::op::RMB6, isa::mode::ZP}},
      {104, {isa::op::PLA, isa::mode::S}},
      {105, {isa::op::ADC, isa::mode::IMM}},
      {106, {isa::op::ROR, isa::mode::A}},
      //{107, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {108, {isa::op::JMP, isa::mode::AI}},
      {109, {isa::op::ADC, isa::mode::A}},
      {110, {isa::op::ROR, isa::mode::A}},
      {111, {isa::op::BBR6, isa::mode::R}},

      {112, {isa::op::BVS, isa::mode::R}},
      {113, {isa::op::ADC, isa::mode::ZPIY}},
      {114, {isa::op::ADC, isa::mode::ZPI}},
      //{115, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {116, {isa::op::STZ, isa::mode::ZPX}},
      {117, {isa::op::ADC, isa::mode::ZPX}},
      {118, {isa::op::ROR, isa::mode::ZPX}},
      {119, {isa::op::RMB7, isa::mode::ZP}},
      {120, {isa::op::SEI, isa::mode::I}},
      {121, {isa::op::ADC, isa::mode::AIY}},
      {122, {isa::op::PLY, isa::mode::S}},
      //{123, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {124, {isa::op::JMP, isa::mode::AII}},
      {125, {isa::op::ADC, isa::mode::AIX}},
      {126, {isa::op::ROR, isa::mode::AIX}},
      {127, {isa::op::BBR7, isa::mode::R}},

      {128, {isa::op::BRA, isa::mode::R}},
      {129, {isa::op::STA, isa::mode::ZPII}},
      //{130, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{131, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {132, {isa::op::STY, isa::mode::ZP}},
      {133, {isa::op::STA, isa::mode::ZP}},
      {134, {isa::op::STX, isa::mode::ZP}},
      {135, {isa::op::SMB0, isa::mode::ZP}},
      {136, {isa::op::DEY, isa::mode::I}},
      {137, {isa::op::BIT, isa::mode::IMM}},
      {138, {isa::op::TXA, isa::mode::I}},
      //{139, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {140, {isa::op::STY, isa::mode::A}},
      {141, {isa::op::STA, isa::mode::A}},
      {142, {isa::op::STX, isa::mode::A}},
      {143, {isa::op::BBS0, isa::mode::R}},

      {144, {isa::op::BCC, isa::mode::R}},
      {145, {isa::op::STA, isa::mode::ZPIY}},
      {146, {isa::op::STA, isa::mode::ZPI}},
      //{147, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {148, {isa::op::STY, isa::mode::ZPX}},
      {149, {isa::op::STA, isa::mode::ZPX}},
      {150, {isa::op::STX, isa::mode::ZPY}},
      {151, {isa::op::SMB1, isa::mode::ZP}},
      {152, {isa::op::TYA, isa::mode::I}},
      {153, {isa::op::STA, isa::mode::AIY}},
      {154, {isa::op::TXS, isa::mode::I}},
      //{155, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {156, {isa::op::STZ, isa::mode::A}},
      {157, {isa::op::STA, isa::mode::AIX}},
      {158, {isa::op::STZ, isa::mode::AIX}},
      {159, {isa::op::BBS1, isa::mode::R}},

      {160, {isa::op::LDY, isa::mode::IMM}},
      {161, {isa::op::LDA, isa::mode::ZPII}},
      {162, {isa::op::LDX, isa::mode::IMM}},
      //{163, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {164, {isa::op::LDY, isa::mode::ZP}},
      {165, {isa::op::LDA, isa::mode::ZP}},
      {166, {isa::op::LDX, isa::mode::ZP}},
      {167, {isa::op::SMB2, isa::mode::ZP}},
      {168, {isa::op::TAY, isa::mode::I}},
      {169, {isa::op::LDA, isa::mode::IMM}},
      {170, {isa::op::TAX, isa::mode::I}},
      //{171, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {172, {isa::op::LDY, isa::mode::A}},
      {173, {isa::op::LDA, isa::mode::A}},
      {174, {isa::op::LDX, isa::mode::A}},
      {175, {isa::op::BBS2, isa::mode::R}},

      {176, {isa::op::BCS, isa::mode::R}},
      {177, {isa::op::LDA, isa::mode::ZPIY}},
      {178, {isa::op::LDA, isa::mode::ZPI}},
      //{179, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {180, {isa::op::LDY, isa::mode::ZPX}},
      {181, {isa::op::LDA, isa::mode::ZPX}},
      {182, {isa::op::LDX, isa::mode::ZPY}},
      {183, {isa::op::SMB3, isa::mode::ZP}},
      {184, {isa::op::CLV, isa::mode::I}},
      {185, {isa::op::LDA, isa::mode::AIY}},
      {186, {isa::op::TSX, isa::mode::I}},
      //{187, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {188, {isa::op::LDY, isa::mode::AIX}},
      {189, {isa::op::LDA, isa::mode::AIX}},
      {190, {isa::op::LDX, isa::mode::AIY}},
      {191, {isa::op::BBS3, isa::mode::R}},

      {192, {isa::op::CPY, isa::mode::IMM}},
      {193, {isa::op::CMP, isa::mode::ZPII}},
      //{194, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{195, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {196, {isa::op::CPY, isa::mode::ZP}},
      {197, {isa::op::CMP, isa::mode::ZP}},
      {198, {isa::op::DEC, isa::mode::ZP}},
      {199, {isa::op::SMB4, isa::mode::ZP}},
      {200, {isa::op::INY, isa::mode::I}},
      {201, {isa::op::CMP, isa::mode::IMM}},
      {202, {isa::op::DEX, isa::mode::I}},
      {203, {isa::op::WAI, isa::mode::I}},
      {204, {isa::op::CPY, isa::mode::A}},
      {205, {isa::op::CMP, isa::mode::A}},
      {206, {isa::op::DEC, isa::mode::A}},
      {207, {isa::op::BBS4, isa::mode::R}},

      {208, {isa::op::BNE, isa::mode::R}},
      {209, {isa::op::CMP, isa::mode::ZPIY}},
      {210, {isa::op::CMP, isa::mode::ZPI}},
      //{211, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{212, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {213, {isa::op::CMP, isa::mode::ZPX}},
      {214, {isa::op::DEC, isa::mode::ZPX}},
      {215, {isa::op::SMB5, isa::mode::ZP}},
      {216, {isa::op::CLD, isa::mode::I}},
      {217, {isa::op::CMP, isa::mode::AIY}},
      {218, {isa::op::PHX, isa::mode::S}},
      {219, {isa::op::STP, isa::mode::I}},
      //{220, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {221, {isa::op::CMP, isa::mode::AIX}},
      {222, {isa::op::DEC, isa::mode::AIX}},
      {223, {isa::op::BBS5, isa::mode::R}},

      {224, {isa::op::CPX, isa::mode::IMM}},
      {225, {isa::op::SBC, isa::mode::ZPII}},
      //{226, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{227, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {228, {isa::op::CPX, isa::mode::ZP}},
      {229, {isa::op::SBC, isa::mode::ZP}},
      {230, {isa::op::INC, isa::mode::ZP}},
      {231, {isa::op::SMB6, isa::mode::ZP}},
      {232, {isa::op::INX, isa::mode::I}},
      {233, {isa::op::SBC, isa::mode::IMM}},
      {234, {isa::op::NOP, isa::mode::I}},
      //{235, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {236, {isa::op::CPX, isa::mode::A}},
      {237, {isa::op::SBC, isa::mode::A}},
      {238, {isa::op::INC, isa::mode::A}},
      {239, {isa::op::BBS6, isa::mode::R}},

      {240, {isa::op::BEQ, isa::mode::R}},
      {241, {isa::op::SBC, isa::mode::ZPIY}},
      {242, {isa::op::SBC, isa::mode::ZPI}},
      //{243, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{244, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {245, {isa::op::SBC, isa::mode::ZPX}},
      {246, {isa::op::INC, isa::mode::ZPX}},
      {247, {isa::op::SMB7, isa::mode::ZP}},
      {248, {isa::op::SED, isa::mode::I}},
      {249, {isa::op::SBC, isa::mode::AIY}},
      {250, {isa::op::PLX, isa::mode::S}},
      //{251, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      //{252, {isa::op::O_INVALID, isa::mode::M_INVALID}},
      {253, {isa::op::SBC, isa::mode::AIX}},
      {254, {isa::op::INC, isa::mode::AIX}},
      {255, {isa::op::BBS7, isa::mode::R}},
    };
    return _;
  }
}